AD9948KCPZRL Analog Devices Inc, AD9948KCPZRL Datasheet - Page 15

• Manufacturer Part Number: AD9948KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9948KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Quadrant
I
II
III
IV
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9948
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver and RG driver current can be adjusted
for optimum rise/fall time into a particular load by using the
DRVCONTROL register (Address x062). The DRVCONTROL
register is divided into five different 3-bit values, each one being
adjustable in 4.1 mA increments. The minimum setting of 0 is
equal to OFF or three-state, and the maximum setting of 7 is
equal to 30.1 mA.
REV. 0
(INTERNAL)
CCDIN
DOUT
SHD
CLI
1 PIXEL PERIOD
NOTES
DEFAULT TIMING VALUES ARE SHOWN: SHDLOC = 0, DOUT PHASE = 0.
HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
H1/H3
H2/H4
t
N–13
Edge Location (Decimal)
0 to 11
12 to 23
24 to 35
36 to 47
N–1
CLIDLY
DOUT
CLI
NOTES
1. DIGITAL OUTPUT DATA (DOUT) PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO ANY OF THE 48 LOCATIONS.
N–12
N
P[0]
t
RISE
SAMPLE PIXEL N
N–11
N+1
t
Figure 7b. Pipeline Delay for Digital Data Output
OD
Figure 6. H-Clock Inverse Phase Relationship
Figure 7a. Digital Output Phase Adjustment
N–10
Table XI. Precision Timing Edge Locations
N+2
FIXED CROSSOVER VOLTAGE
N+3
P[12]
N–9
t
PD
<<
N+4
N–8
PIPELINE LATENCY = 11 CYCLES
t
RISE
–15–
N+5
N–7
Register Value (Decimal)
0 to 11
16 to 27
32 to 43
48 to 59
As shown in Figure 6, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than l ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
Digital Data Outputs
The AD9948 data output phase is programmable using the
DOUTPHASE register (Address x064). Any edge from 0 to 47
may be programmed, as shown in Figure 7a. The pipeline delay
for the digital data output is shown in Figure 7b.
P[24]
N+6
N–6
N+7
N–5
H1/H3
N+8
N–4
P[36]
N+9
N–3
t
PD
N+10
N–2
N+11
P[48] = P[0]
N–1
H2/H4
Register Value (Binary)
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
N+12
N
N+13
N+1
AD9948