AD9948KCPZRL Analog Devices Inc, AD9948KCPZRL Datasheet - Page 25

• Manufacturer Part Number: AD9948KCPZRL
• Description: IC CCD SIGNAL PROCESSOR 40-LFCSP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9948KCPZRL

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Driving the CLI Input
The AD9948’s master clock input (CLI) may be used in two
different configurations, depending on the application. Figure 23a
shows a typical dc-coupled input from the master clock source.
When the dc-coupled technique is used, the master clock signal
should be at standard 3 V CMOS logic levels. As shown in
REV. 0
H1
H3
14
18
H2
Figure 22b. CCD Connections (4 H-Clock)
Figure 22a. CCD Connections (2 H-Clock)
15
19
H4
AD9948
AD9948
H1
H3
18
H1
14
H1
H2
H4
19
15
H2
H2
CCD IMAGER
CCD IMAGER
RG
RG
RG
21
21
RG
SIGNAL
SIGNAL
H2
OUT
OUT
27
27
CCDIN
CCDIN
H1
–25–
Figure 23b, a 1000 pF ac coupling capacitor may be used
between the clock source and the CLI input. In this configura-
tion, the CLI input will self-bias to the proper dc voltage level
of approximately 1.4 V. When the ac-coupled technique is
used, the master clock signal can be as low as ± 500 mV in
amplitude.
AD9948
Figure 23a. CLI Connection, DC-Coupled
Figure 23b. CLI Connection, AC-Coupled
AD9948
CLI
25
CLI
25
1nF
LPF
MASTER CLOCK
ASIC
AD9948
MASTER CLOCK
ASIC