AD9845BJSTZ Analog Devices Inc, AD9845BJSTZ Datasheet - Page 19

• Manufacturer Part Number: AD9845BJSTZ
• Description: IC CCD SIGNAL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9845BJSTZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Supply Voltage Range: 2.7V To 3.6V
• Ic Mounting: SMD
• Tv / Video Case Style: LFCSP
• No. Of Pins: 48
• Msl: MSL 3 - 168 Hours
• Termination Type: SMD
• Sample Rate: 30MSPS
• Data Interface: 3-Wire, Serial
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Digital Ic Case Style: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

D10
X
be used, but clamp noise may increase and the ability to track
low frequency variations in the black level will be reduced.
A/D Converter
The AD9845B uses high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9845B’s ADC uses a 2 V input range. Better noise perfor-
mance results from using a larger ADC full-scale range
(see TPC 3).
AUX1 Mode
For applications that do not require CDS, the AD9845B can be
configured to sample ac-coupled waveforms. Figure 30 shows
the circuit configuration for using the AUX1 channel input
(Pin 36). A single 0.1 mF ac-coupling capacitor is needed between
the input signal driver and the AUX1IN pin. An on-chip dc bias
circuit sets the average value of the input signal to approximately
0.4 V, which is referenced to the midscale code of the ADC.
The VGA gain register provides a gain range of 0 dB to 36 dB in
REV. B
MSB
D9
0
1
1
0.8V
INPUT SIGNAL
SIGNAL
VIDEO
D8
X
0
1
0.4V
0.1 F
D7
X
0
1
??V
0.1 F
AUX2IN
Table VII. VGA Gain Register Used for AUX2 Mode
AUX1IN
D6
X
0
1
Figure 30. AUX1 Circuit Configuration
Figure 31. AUX2 Circuit Configuration
BUFFER
VIDEO CLAMP
0.4V
0.4V
CIRCUIT
5k
LPF
D5
X
0
∑
∑
∑
1
REGISTER
VGA GAIN
VGA
9
–19–
0dB TO 36dB
D4
X
0
1
REGISTER
VGA GAIN
0dB TO 18dB
VGA
this mode of operation (see Figure 29). The VGA gains up the
signal level with respect to the 0.4 V bias level. Signal levels
above the bias level will be further increased to a higher ADC
code, while signal levels below the bias level will be further
decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). An
external 0.1 mF blocking capacitor is used with the on-chip video
clamp circuit to level shift the input signal to a desired refer-
ence level. The clamp circuit automatically senses the most
negative portion of the input signal and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the clamp
level register (see the Serial Interface Timing and Internal Register
Description section). The VGA provides gain adjustment from
0 dB to 18 dB. The same VGA gain register is used, but only
the 9 MSBs of the gain register are used (see Table VII.)
10
8
D3
X
0
1
CLAMP LEVEL
REGISTER
ADC
ADC
D2
X
0
1
D1
X
0
1
CLAMP LEVEL
LSB
D0
X
0
1
MIDSCALE
AD9845B
Gain (dB)
0.0
0.0
∑
∑
∑
18.0