X96012V14I Intersil, X96012V14I Datasheet - Page 20

• Manufacturer Part Number: X96012V14I
• Description: IC CNTRLR UNIV MEM/DAC 14-TSSOP
• Manufacturer: Intersil
• Type: Controllerr

Specifications of X96012V14I

• Input Type: *
• Output Type: *
• Interface: 2-Wire Serial
• Current - Supply: *
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

For example, if the master writes 12 bytes to a 16-byte page
starting at location 11 (decimal), the first 5 bytes are written
to locations 11 through 15, while the last 7 bytes are written
to locations 0 through 6 within that page. Afterwards, the
address counter would point to location 7. If the master
supplies more than 16 bytes of data, then new data
overwrites the previous data, one byte at a time. See
Figure 20.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle.
A Page Write operation cannot be performed on the page at
locations 80h through 8Fh. The next section describes the
special cases within that page.
SIGNAL AT SDA
SIGNALS FROM
SIGNALS FROM
THE MASTER
THE SLAVE
FIGURE 20. EXAMPLE: WRITING 12 BYTES TO A 16-BYTE PAGE STARTING AT LOCATION 11
ADDRESS = 0
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE SLAVE
20
S
T
A
R
T
1
7 BYTES
0
ADDRESS
1
SLAVE
0
S
T
A
R
T
1
ADDRESS = 6
FIGURE 19. PAGE WRITE OPERATION
0
FIGURE 18. BYTE WRITE SEQUENCE
WRITE
ADDRESS
0
1
SLAVE
0
A
C
K
ADDRESS
0
BYTE
WRITE
X96012
A
C
K
ADDRESS = 7
ADDRESS POINTER
ENDS UP HERE
ADDRESS
BYTE
A Page Write operation starting with byte address FFh,
accesses the page between locations 100h and 10Fh. The
first data byte of such operation is written to location 100h.
Writing to Control Registers
The byte at location 80h, 85h, and 86h are written using Byte
Write operations. They cannot be written using a Page Write
operation.
Control bytes 1 through 4, at locations 81h through 84h
respectively, are written during a single operation (see
Figure 21). The sequence must be: a START, followed by a
Slave Address byte, with the R/W bit equal to “0”, followed by
81h as the Address Byte, and then followed by exactly four
Data Bytes, and a STOP condition. The first data byte is
written to location 81h, the second to 82h, the third to 83h,
and the last one to 84h.
A
C
K
DATA BYTE (1)
A
C
K
ADDRESS = 11
2 < n < 16
DATA
BYTE
5 BYTES
5 BYTES
A
C
K
DATA BYTE (N)
ADDRESS = 15
A
C
K
O
S
T
P
A
C
K
O
S
T
P
February 20, 2008
FN8216.3