MAX3693ECJ+ Maxim Integrated Products, MAX3693ECJ+ Datasheet

IC 4:1 SERIALIZER 622MBPS 32TQFP

MAX3693ECJ+

Manufacturer Part Number
MAX3693ECJ+
Description
IC 4:1 SERIALIZER 622MBPS 32TQFP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX3693ECJ+

Function
Serializer
Data Rate
622Mbps
Input Type
LVDS
Output Type
PECL
Number Of Inputs
4
Number Of Outputs
1
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The MAX3693 serializer is ideal for converting 4-bit-
wide, 155Mbps parallel data to 622Mbps serial data in
ATM and SDH/SONET applications. Operating from a
single +3.3V supply, this device accepts low-voltage
differential-signal (LVDS) clock and data inputs for
interfacing with high-speed digital circuitry, and deliv-
ers a 3.3V PECL serial-data output. A fully integrated
PLL synthesizes an internal 622Mbps serial clock from
a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz ref-
erence clock.
The MAX3693 is available in the extended temperature
range (-40°C to +85°C), in a 32-pin TQFP package.
19-4775; Rev 2; 5/04
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
622Mbps SDH/SONET Transmission Systems
622Mbps ATM/SONET Access Nodes
Add/Drop Multiplexers
Digital Cross Connects
GENERATION
(155MHz LVDS CRYSTAL REFERENCE)
OVERHEAD
+3.3V, 622Mbps, SDH/SONET 4:1 Serializer
________________________________________________________________ Maxim Integrated Products
General Description
with Clock Synthesis and LVDS Inputs
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z
PCLKI- PCLKI+ RCLK-
Applications
PD0+
PD0-
PD1+
PD1-
PD2+
PD2-
PD3+
PD3-
PCLKO- PCLKO+
MAX3693
GND
RCLK+
0
= 50Ω)
V
SD-
CC
V
= +3.3V
CC
SD+
CKSET
♦ Single +3.3V Supply
♦ 155Mbps (4-bit-wide) Parallel to
♦ Clock Synthesis for 622Mbps
♦ 215mW Power
♦ Multiple Clock Reference Frequencies
♦ LVDS Parallel Clock and Data Inputs
♦ Differential 3.3V PECL Serial-Data Output
+Denotes lead-free package.
Pin Configuration appears at end of data sheet.
MAX3693ECJ
MAX3693ECJ+
FIL+
FIL-
622Mbps Serial Conversion
(155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
PART
V
CC
= +3.3V
130Ω
1µF
82Ω
Typical Operating Circuit
1µF
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
130Ω
Ordering Information
82Ω
V
MAX3668
CC
= +3.3V
32 TQFP
32 TQFP
PIN-PACKAGE
Features
1

Related parts for MAX3693ECJ+

MAX3693ECJ+ Summary of contents

Page 1

... Power ♦ Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) ♦ LVDS Parallel Clock and Data Inputs ♦ Differential 3.3V PECL Serial-Data Output Applications PART MAX3693ECJ MAX3693ECJ+ +Denotes lead-free package. Pin Configuration appears at end of data sheet +3.3V CC PCLKI- PCLKI+ RCLK- RCLK+ ...

Page 2

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) V .......................................................................-0.5V to +5V CC All Inputs, FIL+, FIL-, PCLKO+, PCLKO- ..............................-0. Output Current LVDS Outputs (PCLKO±)................................................10mA PECL ...

Page 3

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs AC ELECTRICAL CHARACTERISTICS (V = +3V to +3.6V, differential LVDS load = 100Ω ±1%, PECL loads = 50Ω ± wise noted. Typical values are at V ...

Page 4

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs (V = +3.3V, differential LVDS loads = 100Ω ±1%, PECL loads = 50Ω ± SERIAL-DATA OUTPUT EYE DIAGRAM 1.1V 57mV/ div 0.536V 200ps/div PIN NAME 1, ...

Page 5

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs _______________Detailed Description The MAX3693 serializer comprises a 4-bit parallel input register, a 4-bit shift register, control and timing logic, a PECL output buffer, LVDS input/output buffers, and a frequency-synthesizing ...

Page 6

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs PCLKO PCLKI t SU PD_ VALID PARALLEL DATA* SD NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-). *PD3 = D3; PD2 = D2; PD1 = ...

Page 7

SDH/SONET 4:1 Serializer with Clock Synthesis and LVDS Inputs Applications Information Alternative PECL-Output Termination Figure 3 shows alternative PECL output-termination methods. Use Thevenin-equivalent termination when 2V) termination voltage is not available coupling ...

Page 8

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products ...

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