VSC7145XRU-30/C Vitesse Semiconductor Corp, VSC7145XRU-30/C Datasheet - Page 2

• Manufacturer Part Number: VSC7145XRU-30/C
• Description: IC SERDES 10BIT DUAL-SPD 64-PQFP
• Manufacturer: Vitesse Semiconductor Corp

Specifications of VSC7145XRU-30/C

• Function: Serializer/Deserializer
• Data Rate: 2.52Gbps
• Input Type: SSTL (Stub-Series Terminated Logic)
• Output Type: Differential
• Number Of Inputs: 10
• Number Of Outputs: 10
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 907-1006

VSC7145
G E N E R A L D E S C R I P T I O N :
synchronously to the Transmit Byte Clock (TBC) and serializes it
onto the SO differential output at a baud rate which is 10, 20 or 40
times the REFCLK frequency. The VSC7145 samples serial receive
data on the SI input, recovers the clock and data, deserializes it onto
a 10-bit SSTL bus and outputs two recovered clocks at 1/10th or
1/20th of the baud rate. Both disparities of the K28.5 characters are
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For more information on Vitesse Products visit the Vitesse web site
at www.vitesse.com or contact Vitesse Sales at (800) VITESSE
or [e-mail]
V S C 7 1 4 5 B L O C K D I A G R A M :
D U A L S P E E D A U T O N E G O T I AT I O N F I B R E C H A N N E L A P P L I C AT I O N :
©2002 Vitesse Semiconductor Corporation
RBCSYNC
REFRATE
REFCLK0
COMDET
REFCLK1
TXRATE
ENCDET
RXRATE
RX_LOS
EWRAP
Controller
R(0:9)
T(0:9)
Protocol
RBC0
RBC1
TBC
106.25 MHz
Oscillator
10
VSC7145 - Dual Speed 10-bit Serializer/Deserializer
10
T(0-9)
TBC
EN_CDET
EWRAP
TXRATE
R(0:9)
RXRATE
RBC0
RBC1
RX_LOS
COMDET
REFRATE
RBCSYNC
The VSC7145 is a dual-speed Fibre Channel,
Gigabit Ethernet and InfiniBand Serializer/
Deserializer (SerDes) optimized for
performance and power in an industry-
standard pinout. It accepts 10-bits of SSTL,
8B/10B encoded transmit data, latches it
REFCLK
Q D
CAP0
CAP1
SO+
SO-
SI+
SI-
x10/x20/x40
Comma
Detect
Multiplier
Clock
D Q
0.1uF
3.06 / 2.12Gb/s Link
Q
Serial to
Optical
Parallel
TXC P1
TXCAP0
SFP
A
0.1uF
D
to Serial
Parallel
Recovery
Clock
Q D
D Q
detected and used for aligning the serial data to the
parallel output bus. Independent speed selectors control
the transmitter and receiver separately to support
industry-standard automatic speed negotiation protocols.
A combined analog/digital signal detect circuit indicates
the presence of valid signal levels on the SI input. The
VSC7145 contains on-chip PLL circuitry for synthesis of
the bit rate transmit clock, and extraction of the clock
from the received serial stream. The parallel bus of the
VSC7145 is compliant with the High Speed Parallel
Interface (HSPI) standard developed by the T11.2 Fibre
Channel Committee.
0
1
Signal
Detect
=
741 Calle Plano
Camarillo, CA 93012
Tel: [phone]
Fax: [phone]
www.vitesse.com
SO+
SO-
EQAMP
SI+
SI-