DS90C241IVSX/NOPB National Semiconductor, DS90C241IVSX/NOPB Datasheet - Page 18

• Manufacturer Part Number: DS90C241IVSX/NOPB
• Description: IC SERIAL/DESERIAL 24BIT 48-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90C241IVSX/NOPB

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: SERDES24-35USB - BOARD EVALUATION DS90C241
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90C241IVSX

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Applications Information
USING THE DS90C241 AND DS90C124
The
(SERDES) pair sends 24 bits of parallel LVCMOS data over
a serial LVDS link up to 840 Mbps. Serialization of the input
data is accomplished using an on-board PLL at the Serializer
which embeds clock with the data. The Deserializer extracts
the clock/control information from the incoming data stream
and deserializes the data. The Deserializer monitors the in-
coming clockl information to determine lock status and will
indicate lock by asserting the LOCK output high.
DISPLAY APPLICATION
The DS90C241/DS90C124 chipset is intended for interface
between a host (graphics processor) and a Display. It sup-
ports an 18-bit color depth (RGB666) and up to 800 X 480
display formats. In a RGB666 configuration 18 color bits (R
[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits
(VS, HS and DE) along with three spare bits are supported
across the serial link with PCLK rates from 5 to 35 MHz.
TYPICAL APPLICATION CONNECTION
Figure 18
alizer (SER). The LVDS outputs utilize a 100 ohm termination
and 100nF coupling capacitors to the line. Bypass capacitors
are placed near the power supply pins. A system GPO (Gen-
eral Purpose Output) controls the TPWDNB pin. In this appli-
cation the TRFB pin is tied High to latch data on the rising
edge of the TCLK. The DEN signal is not used and is tied High
also. In this application the link is short, therefore the VODSEL
pin is tied Low for the standard LVDS swing. The pre-empha-
sis input utilizes a resistor to ground to set the amount of pre-
emphasis desired by the application.
Figure 19
serializer (DES). The LVDS inputs utilize a 100 ohm termina-
tion and 100nF coupling capacitors to the line. Bypass
capacitors are placed near the power supply pins. A system
GPO (General Purpose Output) controls the RPWDNB pin. In
this application the RRFB pin is tied High to strobe the data
on the rising edge of the RCLK. The REN signal is not used
and is tied High also.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the slope
of the speed vs. I
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still reli-
ably recover data. Various environmental and systematic fac-
tors include:
For a graphical representation of noise margin, please see
Figure
TRANSMISSION MEDIA
The Serializer and Deserializer can be used in point-to-point
configuration, through a PCB trace, or through twisted pair
cable. In a point-to-point configuration, the transmission me-
dia needs be terminated at both ends of the transmitter and
Serializer: TCLK jitter, V
out-of-band noise)
Media: ISI, V
Deserializer: V
16.
DS90C241/DS90C124
shows a typical application of the DS90C241 Seri-
shows a typical application of the DS90C124 De-
CM
CC
CC
noise
curve of CMOS designs.
noise
CC
noise (noise bandwidth and
Serializer/Deserializer
18
receiver pair. Interconnect for LVDS typically has a differential
impedance of 100 Ohms. Use cables and connectors that
have matched differential impedance to minimize impedance
discontinuities. In most applications that involve cables, the
transmission distance will be determined on data rates in-
volved, acceptable bit error rate and transmission medium.
LIVE LINK INSERTION
The Serializer and Deserializer devices support live plug-
gable applications. The automatic receiver lock to random
data “plug & go” hot insertion capability allows the DS90C124
to attain lock to the active data stream during a live insertion
event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS SERDES de-
vices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high fre-
quency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin di-
electrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven es-
pecially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. Ex-
ternal bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz range. To pro-
vide effective bypassing, multiple capacitors are often used
to achieve low impedance between the supply rails over the
frequency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS (LVTTL) signals away from the LVDS lines
to prevent coupling from the LVCMOS lines to the LVDS lines.
Closely-coupled differential lines of 100 Ohms are typically
recommended for LVDS interconnect. The closely coupled