DS90C241IVSX/NOPB National Semiconductor, DS90C241IVSX/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS90C241IVSX/NOPB
• Description: IC SERIAL/DESERIAL 24BIT 48-TQFP
• Manufacturer: National Semiconductor

Specifications of DS90C241IVSX/NOPB

• Function: Serializer/Deserializer
• Data Rate: 840Mbps
• Input Type: LVCMOS
• Output Type: LVDS
• Number Of Inputs: 1
• Number Of Outputs: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• For Use With: SERDES24-35USB - BOARD EVALUATION DS90C241
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DS90C241IVSX

t
t
t
t
t
t
t
t
RxIN_TOL_L Receiver INput TOLerance
RxIN_TOL_R Receiver INput TOLerance
ROS
ROH
HZR
LZR
ZHR
ZLR
DD
DRDL
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at V
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 6: t
Note 7: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 8: The Deserializer PLL lock time (t
Note 9: Specification is guaranteed by characterization and is not tested in production.
Note 10: t
Note 11: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 12: Figures 1, 2, 8, 12, 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 13: Figures 5, 15 show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 14: TxOUT_E_O is affected by pre-emphasis value.
Symbol
DRDL
JIT
(@BER of 10e-9) specifies the allowable jitter on TCLK. t
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT (23:16) Hold Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
Deserializer PLL Lock Time
from Powerdown
Left,
Right,
Parameter
DRDL
) may vary depending on input data patterns and the number of transitions within the pattern.
(Figure
(Figure
(Figure
(Figure
(Note
(Figure
(Note
11)
(Figure
(Note
11)
Conditions
7,
7,
8,
15)
13)
12)
14)
16)
16)
CC
Note
Note
Note
= 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
JIT
not included in TxOUT_E_O parameter.
9,
9,
9)
Note
Note
5
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
5 MHz
35 MHz
5 MHz–35 MHz
5 MHz–35 MHz
Pin/Freq.
DRDL
is specified with an external synchronization pattern.
(0.40)*
(0.40)*
t
t
Min
RCP
RCP
(27/56)*t
(29/56)*t
[4+(3/56)]T
+5.9
Typ
3
3
3
3
5
5
RCP
RCP
[4+(3/56)]T
Max
0.25
0.25
+14
10
10
10
10
50
50
www.national.com
Units
ms
ms
ns
ns
ns
ns
ns
ns
ns
UI
UI