LTC2871IFE#PBF Linear Technology, LTC2871IFE#PBF Datasheet - Page 23

• Manufacturer Part Number: LTC2871IFE#PBF
• Description: IC, RS232-RS485 TXRX, 200MBPS, 5.5V, TSSOP-38
• Manufacturer: Linear Technology

Specifications of LTC2871IFE#PBF

• Device Type: Transceiver
• No. Of Drivers: 2
• Supply Voltage Range: 3V To 5.5V
• Driver Case Style: TSSOP
• No. Of Pins: 38
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Ic Interface Type: RS232, RS485

APPLICATIONS INFORMATION
RS485 Cable Length vs Data Rate
For a given data rate, the maximum transmission dis-
tance is bounded by the cable properties. A typical curve
of cable length vs data rate compliant with the RS485/
RS422 standards is shown in Figure 19. Three regions
of this curve reflect different performance limiting fac-
tors in data transmission. In the flat region of the curve,
maximum distance is determined by resistive losses in
the cable. The downward sloping region represents limits
in distance and data rate due to AC losses in the cable.
Logic Loopback
A loopback mode connects the driver inputs to the re-
ceiver outputs (non-inverting) for self test. This applies to
both RS232 and RS485 transceivers. Loopback mode is
entered when the LB pin is high and the relevant receiver
is enabled.
In loopback mode, the drivers function normally. They can
be disabled with outputs in a Hi-Z state or left enabled to
allow loopback testing in normal operation. Loopback
works in half- or full-duplex mode and does not affect the
termination resistors.
Figure 19. Cable Length vs Data Rate (RS485/RS422
Standard Shown in Vertical Solid Line)
100
10k
1k
10
10k
100k
MAX DATA RATE
RS485/RS422
DATA RATE (bps)
1M
LTC2870/LTC2871
MAX DATA RATE
10M
28701 F19
100M
The solid vertical line represents the specified maximum
data rate in the RS485/RS422 standards. The dashed lines
at 20Mbps show the maximum data rates of the LTC2870
and LTC2871.
Layout Considerations
All V
with very low impedance traces or with a dedicated plane.
A 2.2μF or larger decoupling capacitor (C4 in Figure 13)
must be placed less than 0.7cm away from the V
that is adjacent to the V
0.1μF capacitors to GND can be added on the V
adjacent to the B and V
decoupling capacitor is not direct or if the trace is very
narrow. All GND pins must be connected together and
all V
exposed pad on the bottom of the package. The bypass
capacitor at V
V
1cm of total trace length between the V
Place the charge pump capacitor, C1, directly adjacent to
the SW and CAP pins, with no more than one centimeter
of total trace length to maintain low inductance. Close
placement of the inductor, L1, is of secondary importance
compared to the placement of C1 but should include no
more than two centimeters of total trace length.
The PC board traces connected to high speed signals A/B
and Y/Z should be symmetrical and as short as possible
to minimize capacitive imbalance and maintain good dif-
ferential signal integrity. To minimize capacitive loading
effects, the differential signals should be separated by
more than the width of a trace.
Route outputs away from sensitive inputs to reduce
feedback effects that might cause noise, jitter, or even
oscillations. For example, do not route DI or A/B near the
driver or receiver outputs.
EE
pin that is adjacent to the CAP pin, with no more than
CC
EE
pins must be connected together on the PC board
pins must be connected together, including the
EE
, C3, should be positioned closest to the
LTC2870/LTC2871
L
DD
pins if the connection to the 2.2μF
pin.
EE
and GND pins.
23
CC
CC
pins
28701f
pin