PX1011B-EL1/G,551 NXP Semiconductors, PX1011B-EL1/G,551 Datasheet
PX1011B-EL1/G,551
Specifications of PX1011B-EL1/G,551
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PX1011B-EL1/G-S
PX1011B-EL1/G-S
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PX1011B-EL1/G,551 Summary of contents
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... Media Access Control (MAC) layer devices. The PX1011B is a 2.5 Gbit/s PCI Express PHY with 8-bit data PXPIPE interface. Its PXPIPE interface is a superset of the PHY Interface for the PCI Express (PIPE) specification, enhanced and adapted for off-chip applications with the introduction of a source synchronous clock for transmit and receive data ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Min Typ Max Unit 3.0 3.3 3.6 V 2.3 2 ...
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... Solder process PX1011B-EL1/G Pb-free (SnAgCu solder ball compound) PX1011B-EL1/N SnPb solder ball compound PX1011BI-EL1/G Pb-free (SnAgCu solder ball compound) [1] PX1011B-EL1/Q900 Pb-free (SnAgCu solder ball compound) [1] PX1011B-EL1/Q900 is AEC-Q100 compliant. Contact i2c.support@nxp.com for PPAP. 5. Marking Table 3. Line Table 4. Line [1] Industrial temperature range. PX1011B ...
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... CLK GENERATOR TX I/O REFCLK I/O TX_P TX_N REFCLK_P REFCLK_N Block diagram All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY PCI Express MAC RXDATA [ 7:0 ] RESET_N PCI Express PHY REGISTER 8 10b/8b DECODE ELASTIC ...
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... A RXIDLE SS REFCLK_P REFCLK_N RX_P RX_N TX_P TX_N J VREFS Transparent top view. Fig 3. Ball mapping PX1011B Product data sheet PX1011B-EL1/G PX1011B-EL1/N PX1011BI-EL1/G ball A1 PX1011B-EL1/Q900 index area Transparent top view RXDATA6 RXDATA4 RXDATA3 RXDATA7 RXDATA5 DDD2 SS DDD2 DDA2 DDA1 V TMS V DDD1 DDD1 TCK ...
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... SSTL_2 H6 input SSTL_2 J6 input SSTL_2 All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Table 5 to Table 12. Note that input and Signaling Description differential input receive pair with 50 Ω PCIe I/O on-chip termination ...
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... V CMOS H3 output 3.3 V CMOS All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Description indicates symbol lock and valid data on RX_DATA and RX_DATAK used to communicate completion of several PHY functions including power management state transitions and receiver detection indicates receiver detection of an electrical idle ...
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... Clock and Data Recovery (CDR), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. The PXPIPE interface between the MAC and PX1011B is a superset of the PHY Interface for the PCI Express (PIPE) specification. The following feature have been added: • ...
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... The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum. 8.3 Clocking There are three clock signals used by the PX1011B: • REFCLK is a 100 MHz external reference clock that the PHY uses to generate the 250 MHz data clock and the internal bit rate clock ...
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... P2 state: PHY will enter P1 instead. PX1011B Product data sheet RXCLK Reset All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY 100 MHz 250 MHz © NXP B.V. 2011. All rights reserved. 002aac172 ...
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... Receiver detect - receiver present All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PCI Express stand-alone X1 PHY Receiver TX PLL RXCLK idle on on idle 011b PX1011B RX PLL/CDR on on off - 000b 002aac173 © NXP B.V. 2011. All rights reserved ...
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... RXCLK RXDATA[7:0] Rx-c Rx-d TX_P, TX_N Loopback start Figure 7 shows an example of switching from loopback mode to All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Tx-o Tx-p Tx-q Rx-e Rx-f Rx-g Tx-m Tx-n Rx-e © ...
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... Electrical Idle ordered-set) Electrical Idle All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PCI Express stand-alone X1 PHY Junk includes electrical idle ordered set Junk IDL PX1011B 001aac785 002aac175 © NXP B.V. 2011. All rights reserved ...
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... PHY removed a SKP symbol from a SKP RXCLK active COM RXVALID 000b 001b Clock correction - insert a SKP All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Function description normal operation transmitter in idle loopback mode illegal illegal transmitter in idle illegal ...
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... PX1011B Product data sheet RXCLK active COM RXVALID 000b 010b Function table PXPIPE status interface signals All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY SKP active 000b Output pin RXSTATUS2 RXSTATUS1 RXSTATUS0 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PCI Express stand-alone X1 PHY EDB Rx-d 100b 000b Rx-c Rx-d 111b 000b Figure 13, the PHY is receiving a repeating set of PX1011B Rx-e 001aac780 Rx-e 001aac781 © NXP B.V. 2011. All rights reserved ...
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... RXVALID 000b RXCLK Rx-a Rx-b RXVALID 000b RXCLK D21.5 D21.5 RXVALID RXPOL All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Rx-c EDB Rx-d 110b 000b Rx-c Rx-e Rx-f 101b 000b D10.2 D10.2 © ...
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... TXCLK data K28.5 TXCOMP valid data . SS All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY K28.5 K28.5 K28.5 byte transmitted with negative disparity K28.5− K28.5+ © NXP B.V. 2011. All rights reserved. ...
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... Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from junction to case All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Conditions Min −0.5 for JTAG I/O −0.5 for SSTL_2 I/O − ...
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... SSTL_2; no load for core for high-speed serial I/O and PVT for serializer for serializer 1 clock cycle All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Min Typ Max Unit 3.0 3.3 3 ...
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... Figure 17 on pin REFCLK_N and pin REFCLK_P 1 clock cycle All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Min Typ Max Unit 0.6 - 4.0 V/ns 0 ...
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... Figure 18 see Figure 18 TXCLK PXPIPE INPUT t su(TX)(PXPIPE) RXCLK PXPIPE OUTPUT All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY dV/dt at falling edge 002aad694 Min Typ Max 249.925 250 250.075 249.925 250 250.075 [1] 1 ...
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... Rev. 5 — 18 April 2011 PCI Express stand-alone X1 PHY 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals PX1011B 001aac789 1.1 1.2 001aac790 1.1 1.2 © NXP B.V. 2011. All rights reserved ...
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... REFERENCES JEDEC JEITA MO-205 - - - All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PCI Express stand-alone X1 PHY detail 0.12 0.1 0.08 EUROPEAN PROJECTION PX1011B SOT643-1 ISSUE DATE 00-11-01 02-03-28 © NXP B.V. 2011. All rights reserved ...
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... Solder bath specifications, including temperature and impurities PX1011B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY © NXP B.V. 2011. All rights reserved ...
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... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 22. All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY Figure 22) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... This is a L0s exit failure which may prevent the system from recovering and could cause the PCIe protocol to eventually fail and the link to go down. If this occurs, the PX1011B stays in the exit failure state indefinitely. The receiver can only be re-initiated by applying a hard reset to the PHY, returning it to normal mode ...
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... PHY Interface for the PCI Express Process Voltage Temperature Serial to Parallel Serializer and De-serializer SKiP Stub Series Terminated Logic for 2.5 Volts All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY © NXP B.V. 2011. All rights reserved ...
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... Modifications: Section 14: Errata information added PX1011B v.3 20081020 • Modifications: Added type number PX1011B-EL1/N (affects Section 2.6 “Miscellaneous”, Table 2 “Ordering information”, (new) Table 3 “Leaded package marking”, Figure 2 “Pin configuration for LFBGA81”) PX1011B v.2 20080319 PX1011B v.1 20080213 ...
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... Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY © NXP B.V. 2011. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 18 April 2011 PX1011B PCI Express stand-alone X1 PHY © NXP B.V. 2011. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PX1011B All rights reserved. Date of release: 18 April 2011 Document identifier: PX1011B ...