PX1011B-EL1/G,551 NXP Semiconductors, PX1011B-EL1/G,551 Datasheet - Page 15

• Manufacturer Part Number: PX1011B-EL1/G,551
• Description: IC PCI-EXPRESS X1 PHY 81-LFBGA
• Manufacturer: NXP Semiconductors

Specifications of PX1011B-EL1/G,551

• Package / Case: 81-LFBGA
• Applications: PCI Express MAX to PCI Express PHY
• Interface: JTAG
• Voltage - Supply: 1.2 V
• Mounting Type: Surface Mount
• Input Voltage Range (max): 0.31 V
• Maximum Operating Temperature: + 70 C
• Maximum Power Dissipation: 300 mW
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.2 V
• Supply Current (max): 28 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-4715; 935282113551; PX1011B-EL1/G-S; PX1011B-EL1/G-S

NXP Semiconductors
PX1011B
Product data sheet
8.10 Error detection
The PHY is responsible for detecting receive errors of several types. These errors are
signaled to the MAC layer using the receiver status signals RXSTATUS.
Table 15.
Because of higher level error detection mechanisms (like CRC) built into the data link
layer of PCI Express, there is no need to specifically identify symbols with errors.
However, timing information about when the error occurred in the data stream is
important. When a receive error occurs, the appropriate error code is asserted for one
clock cycle at the point closest to where the error actually occurred.
There are four error conditions that can be encoded on the RXSTATUS signals. If more
than one error should happen to occur on a received byte, the errors are signaled with the
priority shown below.
Operating mode
Received data OK
One SKP added
One SKP removed
Receiver detected
8b/10b decode error
Elastic buffer overflow
Elastic buffer underflow
Receive disparity error
1. 8b/10b decode error
2. Elastic buffer overflow
3. Elastic buffer underflow
4. Disparity error
Fig 10. Clock correction - remove a SKP
RXSTATUS2,
RXSTATUS1,
RXSTATUS0
RXDATA[7:0]
RXVALID
RXCLK
Function table PXPIPE status interface signals
All information provided in this document is subject to legal disclaimers.
active
000b
Rev. 5 — 18 April 2011
COM
010b
000b
SKP
Output pin
RXSTATUS2 RXSTATUS1 RXSTATUS0
L
L
L
L
H
H
H
H
PCI Express stand-alone X1 PHY
active
L
L
H
H
L
L
H
H
PX1011B
© NXP B.V. 2011. All rights reserved.
L
H
L
H
L
H
L
H
002aac176
15 of 32