FW82810 Q862 Intel, FW82810 Q862 Datasheet - Page 19

• Manufacturer Part Number: FW82810 Q862
• Manufacturer: Intel

Specifications of FW82810 Q862

• Lead Free Status / Rohs Status: Not Compliant

3.
Specification Update
R
Added: ACPI Rev 1.0 - Support for Resume from S3 State, Section 4.9.2
The following information is added as Section 4.9.2:
4.9.2
The 82810 chipset enters self-refresh upon entering S3 (Suspend to RAM). The normal sequence is
that the GMCH sends a “Precharge All banks” to SDRAM and then issues an “Enter Self-Refresh”
command prior to actually entering the S3 state. However, the GMCH may issue an "Open Bank"
command between these two commands if the graphics portion is not correctly shut down prior to
entering S3. The “Open Bank” command may adversely affect the memory interface in back-to-
back repetitive S3-S0-S3-S0 testing activities.
There should be no request for access to the memory interface when entering S3. For CPU initiated
transfers, the ICHx guarantees this since it asserts STPCLK#. For I/O based traffic such as PCI
cards, all traffic should be stopped by the O/S, BIOS, and graphics driver combination.
Unified Memory Architecture such as that used in the 82810 chipset requires additional
precautions since the graphics controller shares memory directly with system memory. All graphics
initiated traffic needs to be stopped. The solution is to stop all graphics engines that request
memory resources.
Software must disable all traffic generated by the GMCH graphics engines prior to entering S3.
This includes display screen refresh (SR01 (I/O and memory offset address 3C5h (Index = 01h)),
bit 5 = 1), Overlay (MMADR+68h), hardware cursor (Cursor Control Register, Memory Offset
Address 70080h, bits 2:0 = 000), and the command streamer. The responsibility for this action can
be in the O/S, in the system BIOS, or in the graphics driver.
The standard VGA mode only needs to disable the screen refresh since it doesn't start any other
graphics traffic. Standard VGA drivers normally ensure this prior to entering S3 by setting the
SR01 (I/O and memory offset address 3C5h (Index = 01h)), bit 5 = 1.
ACPI Rev 1.0 - Support for Resume from S3 State
Intel
®
82810 GMCH
19