DS33X11+ Maxim Integrated Products, DS33X11+ Datasheet - Page 4

• Manufacturer Part Number: DS33X11+
• Description: IC MAPPING ETHERNET 144CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33X11+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 144-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.
11.
12.
13.
Rev: 063008
________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
9.1
9.2
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
11.1
11.2
11.3
11.4
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
13.1
13.2
10.1.1
10.1.2
10.2.1
10.2.2
10.2.3
10.2.4
10.3.1
10.3.2
10.3.3
10.4.1
10.7.1
10.7.2
10.8.1
10.8.2
10.8.3
10.8.4
10.8.5
10.8.6
10.8.7
11.1.1
13.1.1
13.2.1
DEVICE REGISTERS................................................................................................................... 105
FUNCTIONAL TIMING ................................................................................................................. 330
OPERATING PARAMETERS ......................................................................................................339
JTAG INFORMATION .................................................................................................................. 363
I
I
NTERFACING TO
NTERFACING TO
R
G
E
A
P
D
VCAT/LCAS R
S
F
F
V
MII/RMII
T
T
T
T
MDIO I
T
T
DDR SDRAM I
AC C
JTAG I
JTAG TAP C
I
NSTRUCTION
UNCTIONAL
UNCTIONAL
HERMAL
RANSMIT AND
RANSMIT AND
RANSMIT AND
RANSMIT AND
RANSMIT AND
THERNET
RBITER
ACKET
ERIAL
OICE
EGISTER
ECAPSULATOR
LOBAL
Global Register Bit Map ..................................................................................................................... 106
MAC Indirect Register Bit Map........................................................................................................... 131
Microport Registers ............................................................................................................................ 147
MAC 1 Interface Access Registers .................................................................................................... 152
MAC 2 Interface Access Registers .................................................................................................... 156
VLAN Control Registers ..................................................................................................................... 160
WAN Extraction and Transmit LAN registers..................................................................................... 164
Receive LAN Register Definitions...................................................................................................... 175
Bridge Filter Registers........................................................................................................................ 188
Arbiter Register Bit Descriptions ........................................................................................................ 189
Transmit VCAT Registers .................................................................................................................. 245
VCAT Receive Register Description .................................................................................................. 252
Serial Interface Transmit and Common Registers............................................................................. 265
Serial Interface Transmit Register Bit Descriptions ........................................................................... 265
Transmit Per Serial Port Register Description ................................................................................... 269
Transmit Voice Port Register Description .......................................................................................... 270
Receive Per Serial Port Register Description .................................................................................... 273
Receive Voice Port Register Description ........................................................................................... 274
MAC Registers ................................................................................................................................... 275
SPI Transmission Format and CPHA Polarity ................................................................................... 330
TAP Controller State Machine ........................................................................................................... 364
SAMPLE:PRELOAD .......................................................................................................................... 367
HARACTERISTICS
P
NTERFACE
NTERFACE
I
NTERFACE
ORT
R
P
R
AND
C
ROCESSOR
EGISTER
B
EGISTERS
I
HARACTERISTICS
NTERFACE
IT
F
SPI I
S
ONTROLLER
R
GMII I
M
UNCTIONAL
ERIAL
M
M
R
R
R
R
R
EGISTERS
NTERFACE
EGISTER
APS
R
AXIM
AXIM
ECEIVE
ECEIVE
ECEIVE
ECEIVE
ECEIVE
EGISTERS
NTERFACE
....................................................................................................................348
....................................................................................................................362
R
D
NTERFACES
................................................................................................................106
................................................................................................................189
I
EGISTERS
EFINITIONS
NTERFACE
(E
T1/E1 T
T3/E3 T
—M
R
NCAPSULATOR
...........................................................................................................367
EGISTERS
GMII I
MII I
RMII I
WAN I
V
.........................................................................................................245
S
........................................................................................................353
T
OICE
ICROPROCESSOR
TATE
IMING
....................................................................................................236
....................................................................................................341
T
NTERFACE
RANSCEIVERS
RANSCEIVERS
IMING
NTERFACE
NTERFACE
................................................................................................265
NTERFACE
P
...............................................................................................141
T
..............................................................................................336
ORT
M
D
IMING
...........................................................................................164
ACHINE
IAGRAMS
........................................................................................330
I
NTERFACE
) R
...................................................................................333
...................................................................................344
EGISTERS
................................................................................342
................................................................................346
................................................................................349
D
............................................................................101
............................................................................103
............................................................................335
B
ESCRIPTION
US
.....................................................................351
I
NTERFACE
.................................................................230
.........................................................364
T
IMING
........................................355
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