UJA1069TW24/5V0/C, NXP Semiconductors, UJA1069TW24/5V0/C, Datasheet - Page 40

• Manufacturer Part Number: UJA1069TW24/5V0/C,
• Description: IC LIN FAIL-SAFE 24HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/5V0/C,

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935285413512

NXP Semiconductors
7. Limiting values
Table 24.
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND.
[1]
[2]
[3]
[4]
[5]
[6]
UJA1069_4
Product data sheet
Symbol
V
V
V
V
I
T
T
T
V
WAKE
stg
amb
vj
BAT42
BAT14
DC(n)
trt
ESD
Only relevant if V
In accordance with IEC 60747-1. An alternative definition of virtual junction temperature is: T
is a fixed value to be used for the calculation of T
ambient temperature (T
Human Body Model (HBM): C
Only applies for pin BAT42 if C
ESD performance according to IEC 61000-4-2 (C
was verified by an external test house. The following results were obtained:
a) Equal or better than 4 kV (unaided)
b) Equal or better than 20 kV for pin LIN (using external ESD protection: NXP Semiconductors PESD1LIN diode).
Machine Model (MM): C
Limiting values
Parameter
BAT42 supply voltage
BAT14 supply voltage
DC voltage on pins
transient voltage at pin LIN
DC current at pin WAKE
storage temperature
ambient temperature
virtual junction temperature
electrostatic discharge voltage
V1
V3 and SYSINH
INH/LIMP
SENSE
WAKE
LIN and RTLIN
TXDL, RXDL, SDO, SDI, SCK, SCS,
RSTN, INTN and EN
TEST
WAKE
< V
amb
MM
GND
).
= 200 pF; L
HBM
BAT42
0.3 V; current will flow into pin GND.
= 100 pF; R
(connected between pin BAT42 and GND)
MM
= 0.75 H; R
HBM
vj
IEC
. The rating for T
= 1.5 k .
Rev. 04 — 28 October 2009
= 150 pF, R
Conditions
load dump; t
V
with respect to any other pin
in accordance with
ISO 7637-3
HBM
MM; at any pin
MM
BAT42
continuous
load dump; t
at pins LIN, RTLIN,
WAKE, BAT42, V3,
SENSE; with respect to
GND
at any other pin
= 10 .
IEC
V
vj
= 330 ) of pins LIN, RTLIN, WAKE and BAT42 with respect to GND
BAT14
limits the allowable combinations of power dissipation (P
500 ms
500 ms
1 V
10 nF; otherwise V
[4][5]
[1]
[2]
[3]
[6]
vj
= T
LIN fail-safe system basis chip
Min
-
-
0.3
0.3
0.3
1.5
0.3
0.3
1.5
60
0.3
0.3
150
15
55
40
40
8.0
2.0
200
amb
ESD
+ P
=
d
4 kV for pin BAT42.
R
th(vj-amb)
Max
+60
+60
+33
+45
+5.5
V
V
V
+60
+60
V
+15
+100
-
+150
+125
+150
+8.0
+2.0
+200
UJA1069
BAT42
BAT42
BAT42
V1
© NXP B.V. 2009. All rights reserved.
+ 0.3
, where R
+ 0.3
+ 0.3
+ 1.2
d
) and
40 of 64
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
kV
kV
V
th(vj-amb)
C
C
C