W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet
W83627EHG
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W83627EHG Summary of contents
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... W83627EHF/EF W83627EHG/EG NUVOTON LPC I/O Note: This document is both for UBC and UBH version except the specified descriptions Date: April 2009 Revision: 1.94 ...
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... GPIO-1 and GPIO-4 with WDTO# / SUSLED / PLED multi-function................................27 5.10 POWER PINS ..................................................................................................................... 27 6. CONFIGURATION REGISTER ACCESS PROTOCOL ........................................................... 29 6.1 Configuration Sequence ..................................................................................................... 30 6.1.1 Enter the Extended Function Mode..................................................................................31 6.1.2 Configure the Configuration Registers .............................................................................31 6.1.3 Exit the Extended Function Mode ....................................................................................31 W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -I- Version 1.94 ...
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... SMI# interrupt mode ........................................................................................................... 54 7.7.1 Voltage SMI# mode..........................................................................................................54 7.7.2 Fan SMI# mode................................................................................................................54 7.7.3 Temperature SMI# mode .................................................................................................55 7.7.3.1. Temperature sensor 1(SYSTIN) SMI# interrupt has 3 modes ........................................................... 55 7.7.3.2. Temperature sensor 2(CPUTIN) and sensor 3(AUXTIN) SMI# interrupt has two modes .................. 57 W83627EHF/EF, W83627EHG/ /Pentium III thermal diode .................................................. ...
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... AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) 74 7.9.23 Tolerance of Target Temperature or Target Speed Register - Index 14h (Bank 0) ..........75 7.9.24 AUXFANOUT Stop Value Register - Index 15h (Bank 0).................................................76 W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -III- Version 1.94 ...
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... Diode Selection Register - Index 59h (Bank 0) ................................................................92 7.9.51 Reserved - Index 5Ah-5Ch (Bank 0) ................................................................................93 7.9.52 VBAT Monitor Control Register - Index 5Dh (Bank 0) ......................................................93 7.9.53 Reserved Register - Index 5Eh-5Fh (Bank 0) ..................................................................94 7.9.54 CPUFANOUT1 PWM Output Frequency Configuration Register - Index 60h (Bank 0)....94 W83627EHF/EF, W83627EHG/EG (Bank 0)...................................................................... ...
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... AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2).....105 7.9.77 AUXTIN Temperature Sensor Over-temperature (High Byte) Register - Index 55h (Bank 2) 106 7.9.78 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2) 106 W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -V- Version 1.94 ...
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... Tape Drive Register (TD Register) (Read base address + 3) ........................................136 8.2.5 Main Status Register (MS Register) (Read base address + 4) ......................................137 8.2.6 Data Rate Register (DR Register) (Write base address + 4)..........................................137 8.2.7 FIFO Register (R/W base address + 5)..........................................................................139 8.2.8 Digital Input Register (DI Register) (Read base address + 7) ........................................141 W83627EHF/EF, W83627EHG/ ...
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... EPP Version 1.7 Operation .............................................................................................................. 163 10.3 Extended Capabilities Parallel (ECP) Port........................................................................ 164 10.3.1 ECP Register and Bit Map .............................................................................................164 10.3.2 Data and ecpAFifo Port..................................................................................................166 10.3.3 Device Status Register (DSR)........................................................................................167 W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -VII- Version 1.94 ...
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... Hardware GATEA20/Keyboard Reset Control Logic........................................................ 180 11.5.1 KB Control Register .......................................................................................................180 11.5.2 Port 92 Control Register.................................................................................................181 12. POWER MANAGEMENT EVENT........................................................................................... 182 12.1 Resume Reset Logic......................................................................................................... 182 12.2 PWROK Generation.......................................................................................................... 183 13. SERIALIZED IRQ.................................................................................................................... 186 13.1 Start Frame ....................................................................................................................... 186 13.2 IRQ/Data Frame................................................................................................................ 187 13.3 Stop Frame ....................................................................................................................... 189 W83627EHF/EF, W83627EHG/EG - VIII - ...
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... Clock Input Timing .........................................................................................................248 18.3.3 SMBus Timing................................................................................................................250 18.3.4 Floppy Disk Drive Timing ...............................................................................................251 18.3.5 UART/Parallel Port.........................................................................................................252 18.3.5.1. Modem Control Timing ..................................................................................................................... 254 18.3.6 Parallel Port Mode Parameters ......................................................................................255 18.3.7 Parallel Port ...................................................................................................................256 W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -IX- Version 1.94 ...
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... Send Data to Mouse......................................................................................................................... 268 18.3.8.7. Receive Data from Mouse................................................................................................................ 268 18.3.9 GPIO Timing Parameters...............................................................................................268 18.3.9.1. GPIO Write Timing ........................................................................................................................... 269 18.4 LPC Timing ....................................................................................................................... 270 18.5 Reset Timing ..................................................................................................................... 271 19. TOP MARKING SPECIFICATION .......................................................................................... 272 20. PACKAGE SPECIFICATION .................................................................................................. 273 21. REVISION HISTORY .............................................................................................................. 274 W83627EHF/EF, W83627EHG/ ...
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... General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a predefined alternate function. W83627EHF/EHG supports hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan W83627EHF/EF, W83627EHG/EG Each UART includes a 16-byte send/receive FIFO, a Publication Release Date: April 7, 2009 -1- They Version 1 ...
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... Special care might be applied during layout stage or the IC will fail even though its intended function is workable. W83627EHF/EF, W83627EHG/EG TM ” functions. Smart Fan can make system more stable and user © ...
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... Built-in address mark detection circuit to simplify the read electronics • FDD anti-virus functions with software write protect and FDD write enable signal (write data signal was forced to be inactive) • Support one 3.5-inch or 5.25-inch floppy disk drive W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -3- Version 1.94 ...
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... Support SHARP ASK-IR protocol with maximum baud rate up to 57,600 bps Parallel Port • Compatible with IBM parallel port • Support PS/2 compatible bi-directional parallel port • Support Enhanced Parallel Port (EPP) - Compatible with IEEE 1284 specification • Support Extended Capabilities Port (ECP) - Compatible with IEEE 1284 specification W83627EHF/EF, W83627EHG/ ...
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... Bit Timer/ Counter • Support binary and BCD arithmetic • 6 MHz, 8 MHz, 12 MHz MHz operating frequency General Purpose I/O Ports • 48 programmable general purpose I/O ports W83627EHF/EF, W83627EHG/ -2, Phoenix MultiKey/42 Publication Release Date: April 7, 2009 -5- or customer code Version 1.94 ...
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... Over temperature indicate output • Issue SMI#, OVT# to activate system protection TM • Nuvoton Hardware Doctor • 6 VID inputs / outputs 2 • Provide I C interface to read/write registers Package W83627EHF/EF, W83627EHG/ “Thermal Cruise TM III function TM support - ” and “Speed II/III/4 thermal diode output ...
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... LRESET#, LCLK, LFRAME#, LAD[3:0], LDRQ#, SERIRQ Game Joystick interface Port signals MSI MIDI MSO General-purpose GPIO I/O pins Keyboard/Mouse KBC data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC URA PRT ACPI W83627EF/EG Publication Release Date: April 7, 2009 -7- Floppy drive interface signals Serial port A, B interface signals ...
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... Game signals Port MSI MIDI MSO General-purpose I/O pins GPIO Hardware monitor HM channel and Vref Keyboard/Mouse KBC data and clock W83627EHF/EF, W83627EHG/EG LPC Interface FDC URA PRT ACPI W83627EHF/EHG - 8 - Floppy drive interface signals Serial port A, B interface signals IRRX IRTX Printer port ...
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... GP17/GPSA2 122 122 GP16/GPSB2 GP16/GPSB2 GP15/GPY1 GP15/GPY1 123 123 124 124 GP14/GPY2 GP14/GPY2 125 125 GP13/GPX2 GP13/GPX2 126 126 GP12/GPX1 GP12/GPX1 127 127 GP11/GPAB1 GP11/GPAB1 128 128 GP10/GPSA1 GP10/GPSA1 Pin Layout for W83627EHF/EHG W83627EHF/EF, W83627EHG/EG 3VSB 3VSB 3VSB 3VSB VBAT VBAT ...
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... W83627EHF/EF, W83627EHG/EG 3VCC 3VCC 3VCC 3VCC 3VCC 3VSB 3VSB 3VSB 3VSB 3VSB 103 103 103 103 103 104 104 104 104 104 105 105 105 105 105 106 106 106 106 106 107 107 107 107 107 108 108 108 108 ...
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... Open-drain output pin with 24 mA sink capability 24 5.1 LPC Interface SYMBOL PIN I/O IN IOCLK 18 t OUT PME W83627EHF/EF, W83627EHG/EG FUNCTION System clock input, which is selective by the register according to the input frequency either 24MHz or 48MHz. Default is 48MHz. Generated PME event. Publication Release Date: April 7, 2009 -11- Version 1.94 ...
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... Step output pulses. This active low open drain output produces a pulse to OD STEP move the head to another track. W83627EHF/EF, W83627EHG/EG FUNCTION PCI clock 33 MHz input. Encoded DMA Request signal. Serial IRQ Input/Output. These signal lines communicate address, control, and data information over the LPC bus between a host and a peripheral. ...
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... This input pin can be pulled up internally KΩ(± IN DSKCHG# 17 tsu 50%) . The resistor also can be disabled / enabled by bit 7 of LD0-CRF0 (FIPURDWN). Default is disabled. W83627EHF/EF, W83627EHG/EG FUNCTION This active low Schmitt input from the disk drive Publication Release Date: April 7, 2009 -13- Version 1.94 ...
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... Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. PRINTER MODE: SLIN Output line for detection of printer selection. Refer to the OUT / SLIN description of the parallel port for the definition of this pin in ECP and EPP mode. W83627EHF/EF, W83627EHG/EG FUNCTION - 14 - ...
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... I/O PD4 38 Parallel port data bus bit 4. 12ts parallel port for the definition of this pin in ECP and EPP mode. W83627EHF/EF, W83627EHG/EG FUNCTION Refer to the description of the Refer to the description of the Refer to the description of the Refer to the description of the Refer to the description of the ...
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... Data Set Ready. An active low signal indicates the modem or IN DSRA# data set is ready to establish a communication link and transfer t 50 data to the UART. I/OD GP66 General purpose I/O port 6 bit 6. 12t W83627EHF/EF, W83627EHG/EG FUNCTION Refer to the description of the Refer to the description of the Refer to the description of the FUNCTION - 16 - ...
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... Serial Input used to receive serial data through the IN SINA t communication link. 53 I/OD GP63 General purpose I/O port 6 bit 3. 12 Serial Input used to receive serial data through the IN SINB 82 t communication link. W83627EHF/EF, W83627EHG/EG FUNCTION A 1 kΩ is reserved to pull down Publication Release Date: April 7, 2009 -17- and a 1 Version 1.94 ...
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... General purpose I/O port 6 bit 0. 12 Ring Indicator. An active low signal indicates that a ring signal is IN RIB# t being received from the modem or data set. 85 I/OD GP40* General purpose I/O port 4 bit 0. 12 W83627EHF/EF, W83627EHG/EG FUNCTION A 1 kΩ is reserved to pull down - 18 - and a 1 kΩ is ...
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... IN CASEOPEN VIN4 95 AIN W83627EHF/EF, W83627EHG/EG FUNCTION Gate A20 output. This pin is high after system reset. (KBC P21) Keyboard reset. This pin is high after system reset. (KBC P20) Keyboard Clock. General purpose I/O port 2 bit 7. Keyboard Data. General purpose I/O port 2 bit 6. ...
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... PCIRST) VID5 105 VID4 106 VID3 107 I/O VID input detect, also with output control. 12 VID2 108 VID1 109 VID0 110 AUXFANIN1 58 I +3.3V amplitude fan tachometer input. 12ts AUXFANIN0 111 I +3.3V amplitude fan tachometer input. 12ts W83627EHF/EF, W83627EHG/EG FUNCTION - 20 - ...
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... IN GPSB1 ts 127 I/OD GP11** 12ts W83627EHF/EF, W83627EHG/EG FUNCTION 0V to +3.3V amplitude fan tachometer input. (Default) MIDI serial data input. General purpose I/O port 2 bit 1. DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. ...
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... I/OD 12ts MSO 120 OUT 12t W83627EHF/EF, W83627EHG/EG FUNCTION Joystick II timer pin. This pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 2. Joystick II timer pin. This pin connects to X positioning variable resistors for the Joystick. (Default) General purpose I/O port 1 bit 3 ...
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... SDA I/OD 12t RSTOUT4# 88 OUT 12 W83627EHF/EF, W83627EHG/EG FUNCTION DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. General purpose I/O port 2 bit 0. FUNCTION Panel Switch Input. This pin is high active with an internal pull down resistor ...
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... GP21 119 I/OD 12ts CPUFANIN1 I/O 12ts W83627EHF/EF, W83627EHG/EG FUNCTION General purpose I/O port 3 bit 4. FUNCTION General purpose I/O port 2 bit 0. DC/PWM fan output control. CPUFANOUT0 & AUXFANOUT are default PWM Mode, CPUFANOUT1 & SYSFANOUT are default DC Mode. MIDI serial data output. ...
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... RSTOUT3# OUT Secondary LRESET# output 3. 12 SDA I/OD Serial bus bi-directional Data. 12t W83627EHF/EF, W83627EHG/EG FUNCTION MIDI serial data input. (Default) General purpose I/O port 2 bit 2. General purpose I/O port 2 bit 3. General purpose I/O port 2 bit 4. PS2 Mouse Data. General purpose I/O port 2 bit 5. ...
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... PSON# OD This pin generates the PWRCTL# signal while the power failure. 12 GP54 I/OD General purpose I/O port 5 bit 4. 12t 71 PWROK OD This pin generates the PWROK signal while the VCC come in. 12 W83627EHF/EF, W83627EHG/EG FUNCTION FUNCTION A 1 kΩ is reserved to pull down - 26 - ...
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... POWER PINS SYMBOL PIN 3VSB 61 VBAT 74 3VCC 12,28,48 W83627EHF/EF, W83627EHG/EG FUNCTION (This pin is push-pull output (This pin is push-pull output mode) state. This pin is pulse output, active low FUNCTION This GPxx* can be served GPIO or Watchdog timer output signal. This GPxx** can be served GPIO or Power LED output signal. ...
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... Analog +3.3V power input. Internally supplier to all analog AVCC 114 circuitry. Internally connected to all analog circuitry. The ground reference AGND 117 for all analog inputs. GND 20,55 Ground. W83627EHF/EF, W83627EHG/ ...
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... Logical Device Logical Device Configuration Configuration # Devices of I/O Base Address LOGICAL DEVICE NUMBER W83627EHF/EF, W83627EHG/EG One Per One Per Logical Device Logical Device #C #C FUNCTION FDC Parallel Port UART A Publication Release Date: April 7, 2009 -29- I/O BASE ADDRESS 100h ~ FF8h 100h ~ FF8h 100h ~ FF8h Version 1 ...
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... Check Pass key Check Pass key Check Pass key the data Is the data “87h”? “87h”? Extended Function Extended Function W83627EHF/EF, W83627EHG/EG FUNCTION UART B Reserved Keyboard Controller Reserved WDTO# & PLED GPIO & SUSLED ACPI Hardware Monitor Any other I/O transition cycle ...
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... EFIR is located at 2Eh and the EFDR is located at 2Fh. If the HEFRAS (CR26 bit 6) is set, 2Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh. ;----------------------------------------------------- ; Enter the Extended Function Mode ;----------------------------------------------------- MOV DX, 2EH MOV AL, 87H OUT DX, AL W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -31- Version 1.94 ...
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... Read Only 21h Read Only 22h R/W 23h R/W 24h R/W 25h R/W 26h R/W 27h W83627EHF/EF, W83627EHG/EG DEFAULT VALUE DESCRIPTION Software Reset 00h Logical Device A0h Chip ID, MSB 2xh Chip ID, LSB FFh Device Power Down 00h Immediate Power Down 0100_0ss0b ...
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... The application software could be Nuvoton's Hardware Doctor management application software. Also the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and to activate one programmable and masked interrupts. W83627EHF/EF, W83627EHG/EG DEFAULT VALUE DESCRIPTION 50h ...
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... The other higher bits of these ports are set by W83627EHF/EHG itself. The general decoded address is set to port 295h and port 296h. These two ports are described as following: Port 295h: Index port. Port 296h: Data port. The register structure is showed as the Figure 7.1 W83627EHF/EF, W83627EHG/ ...
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... Figure 7.1 : LPC interface access diagram 2 7.2 interface 2 The second interface uses I C Serial Bus. W83627EHF/EHG has a programmable serial bus address. It defined at Index 48h. W83627EHF/EF, W83627EHG/EG Smart Fan Configuration Registers 00h-1Fh Configuration Register 40h Interrupt Status Registers 41h, 42h SMI# Mask Registers ...
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... PC monitoring would most often be connected to power suppliers. The CPU Vcore voltage, VBAT(pin 74), 3VSB(pin 61), 3VCC(pin 12) , AVCC(pin 114) voltage can directly connected to these analog inputs. The +12V voltage inputs should be reduced a factor with external resistors obtain the input range. As Figure 7.2 shows. W83627EHF/EF, W83627EHG/ ...
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... The value of R3 and R4 can be selected to 232K Ohms and 10K Ohms, respectively, when the input voltage V is -12V. The node voltage of VIN1 can be subject to less than 2.048V for the maximum input 1 range of the 8-bit ADC. W83627EHF/EF, W83627EHG/EG AVCC VBAT Power Inputs VSB ...
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... LSB from the Bank1/Bank2 Index[51h] bit 7. The format of the temperature data is show in Table 7.1. TEMPERATURE 8-BIT DIGITAL OUTPUT 8-BIT BINARY +125°C 0111,1101 +25°C 0001,1001 +1°C 0000,0001 +0.5°C - +0°C 0000,0000 W83627EHF/EF, W83627EHG/EG Ω K ≅ , where VCC is set to 3.3V Ω 008 ...
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... AGND(pin 117) and the pin D+ is connected to temperature sensor pin in the W83627EHF/EHG. The resistor R=15K ohms should be connected to VREF to supply the diode bias current and the bypass capacitor C=2200pF should be added to filter the high frequency noise. Pentium II/III/IV CPU Therminal Diode W83627EHF/EF, W83627EHG/EG 9-BIT DIGITAL OUTPUT 8-BIT HEX 9-BIT BINARY - 1,1111,1111 FFh ...
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... Index 5Dh.bit5~7 which are three bits for divisor. That provides very low speed fan counter such as power supply fan. The followed table is an example for the relation of divisor, RPM, and count. Nominal Divisor RPM 1 8800 4400 2 (default) 4 2200 8 1100 16 550 32 275 64 137 W83627EHF/EF, W83627EHG/EG × Count × RPM Divisor × RPM × Count Divisor ...
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... The sample rate of the W83627EHF/EHG is 22.5 KHz. 24 cycles are needed to complete the ADC conversion of the temperature (worst case), and 16 cycles are needed for the ADC conversion of the voltage. The W83627EHF/EHG has 10 voltage sets and 3 temperature sets. W83627EHF/EF, W83627EHG/EG Time per Counts ...
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... The monitor time of the 3 temperature sets 0.044mS = 3.168 ms The 10 voltage sets 0.044 ms = 7.04 ms Total conversion time = 3.168 + 7.04 = 10.208 ms Please note that the suggested time interval for the most updated data is 20 ms. W83627EHF/EF, W83627EHG/ ...
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... Once the temperature exceeds the setting high limit temperature ( 58°C), the fan will be turned on with a specific speed set by BIOS (ex: 20% output) and automatically controlled its output with the temperature varying. Three conditions may occur : W83627EHF/EF, W83627EHG/EG Pin 115 CPUFANOUT0 Pin 116 SYSFANOUT ...
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... In other words, If “current temperature” > “High Limit”, increase fan speed; If “current temperature” < “Low Limit”, decrease fan speed; Otherwise, keep the fan speed. Figure 7.6 PWM fan mode and Figure 7.7 DC fan mode illustrate the Thermal Cruise mode W83627EHF/EF, W83627EHG/EG Figure 7 ...
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... Fan output will be increased to keep the count less than the high limit. Otherwise, if current fan speed is less than the low limit(ex. 160-10), Fan output will be decreased to keep the count higher than the low limit. See Figure 7.8 example. W83627EHF/EF, W83627EHG/EG Figure 7.7 AUXFANIN ...
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... Temperature 27H Current AUX Bank2 Temperature 50h,51h Current Bank0 CPUFANOUT0 03h Output Value Current Bank0 SYSFANOUT 01h W83627EHF/EF, W83627EHG/EG C Figure 7.8 REGISTER NAME ATTRIBUTE CPUTIN Temperature Read only Sensor SYSTIN Temperature Read only Sensor AUXTIN Temperature Read only Sensor CPUFANOUT0 Output ...
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... AUXFANOUT CR[13h] CR[14h] Bit0-3 CPUFANOUT1 CR[63h] CR[62h] Bit0-3 Table 7.3-3 Relative Register-at Speed Cruise Mode of Smart Fan I control mode THERMAL-CRUISE TARGET-SPEED MODE COUNT W83627EHF/EF, W83627EHG/EG REGISTER NAME ATTRIBUTE AUXFANOUT1 Output FFh Value Select CPUFANOUT1 Output FFh Value Select START- STOP KEEP UP VALUE MIN ...
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... Pin120 (CPUFANOUT1) pairs with Pin104 (SYSTIN), Pin103 (CPUTIN), or Pin102 (AUXTIN), which is defined in Bank0 Index 4Ah.bit7~6. Pin 103 CPUTIN Pin 104 SYSTIN Pin 102 AUXTIN Figure 7.9, 7.10, and 7.11 illustrate SMART FAN described as follows: W83627EHF/EF, W83627EHG/EG CR[07h] CR[12h] CR[0Eh] Bit0-3 Bit5 CR[07h] ...
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... Tolerance) then, the fan speed remains constant. Otherwise, fan speed slows down by one step again. Target Temperature then dynamically shifts to (Target Temperature 1 － Temperature Tolerance), and new Target Temperature again, named Target Temperature 2, is formed. W83627EHF/EF, W83627EHG/EG TM III. Target Temperature, Temperature ...
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... Max. Fan Output Max. Fan Output Max. Fan Output Min. Fan Output Min. Fan Output Min. Fan Output Tar. - Tol. Tar. - Tol. Tar. - Tol. W83627EHF/EF, W83627EHG/EG must be an integer; otherwise, it may lead to register overflow. Setting Setting Setting Tolerance Tolerance Tolerance Tar. + Tol. ...
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... Output Value Step Step Min. Fan Output Min. Fan Output Tar 2 Tar 2 Tar 3 Tar 3 TM 7.6.4 Smart Fan III Mode W83627EHF/EF, W83627EHG/EG Tolerance Tolerance (Max. Fan output – Initial output) (Max. Fan output – Initial output Integer Integer Tar 1 Tar 1 Tar 3 ...
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... Output Value Table 7.4-2 Relative Register-at Smart Fan TM Smart Fan III Target Mode Temperature CPUFANOUT0 CR[06h] CPUFANOUT1 CR[63h] W83627EHF/EF, W83627EHG/EG TM III mode TM III Mode REGISTER NAME ATTRIBUTE CPUTIN Temperature Read only Sensor SYSTIN Temperature Read only Sensor AUXTIN Temperature Read only ...
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... TM Smart Fan III Output Step Mode CPUFANOUT0 CR[68h] CPUFANOUT1 CR[6Ah] W83627EHF/EF, W83627EHG/EG Step Down Step Up Keep Min. Fan Time Time Output value CR[0Eh] CR[0Fh] CR[12h] bit 4 CR[0Eh] CR[0Fh] CR[12h] bit 6 Publication Release Date: April 7, 2009 -53- Version 1.94 ...
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... Status Register. (Figure 7.13) High limit Low limit SMI *Interrupt Reset when Interrupt Status Registers are read Figure 7.12 W83627EHF/EF, W83627EHG/EG Fan Count limit SMI Figure 7. ...
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... Temperature exceeding T causes an interrupt and then temperature going below T O cause an interrupt. Once an interrupt event has occurred by exceeding T an interrupt will not occur again until the temperature exceeding T W83627EHF/EF, W83627EHG/EG (Over Temperature) Limit causes then reset, if the temperature remains above the O ...
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... T HYST 127 SMI *Interrupt Reset when Interrupt Status Registers are read Figure 7. HYST SMI# *Interrupt Reset when Interrupt Status Registers are read W83627EHF/EF, W83627EHG/ HYST SMI Figure 7. Figure 7. ...
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... HYST HYST SMI *Interrupt Reset when Interrupt Status Registers are read Figure 7.17 W83627EHF/EF, W83627EHG/EG , the interrupt will occur again when the next conversion has HYST and not reset, the interrupts will O , then reset, if the temperature HYST SMI Figure 7 ...
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... T HYST To T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) *Interrupt Reset when Temperature sensor registers are read W83627EHF/EF, W83627EHG/EG , then OVT# reset, and then temperature O , the OVT# will not be activated again.(Figure 7.19 Figure 7. then reset, if the O ...
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... Bit7: Reserved Bit 6-0: Read/Write Bit 7 Bit 6 Reserved (Power On default 0) A6 7.9.2 Data Port (Port x6h) Data Port: Port x6h Power on Default Value 00h Attribute: Read/write Size: 8 bits W83627EHF/EF, W83627EHG/ Data Bit 5 Bit 4 Bit 3 Bit 2 Address Pointer (Power On default 00h Publication Release Date: April 7, 2009 ...
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... Set to 1, select 180 KHz. Bit 6-0: SYSFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider W83627EHF/EF, W83627EHG/ Data ...
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... SYSFANOUT be programmed as DC Voltage output (Bank0 Index 04h.bit0 is 1) Bit 7-2: SYSFANOUT voltage control. Bit 1-0: Reserved. OUTPUT Voltage = If AVCC= 3.3V , output voltage table is BIT BIT BIT BIT BIT BIT W83627EHF/EF, W83627EHG/EG Input Clock = Pre_Scale SYSFANOUT Value FANOUT AVCC * 64 OUTPUT BIT BIT BIT BIT VOLTAGE 0.05 ...
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... BIT BIT BIT BIT BIT BIT W83627EHF/EF, W83627EHG/EG OUTPUT BIT BIT BIT BIT VOLTAGE BIT BIT OUTPUT 3 2 VOLTAGE 2.58 ...
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... Bit 6-0: CPUFANOUT0 PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider W83627EHF/EF, W83627EHG/EG OUTPUT BIT BIT BIT BIT VOLTAGE ...
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... Bit 7-2: CPUFANOUT0 voltage control. Bit 1-0: Reserved. OUTPUT Voltage = Note. See the Table 7.4 7.9.7 FAN Configuration Register I - Index 04h (Bank 0) Register Location: 04h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/EG Input Clock Pre_Scale Divider CPUFANOUT0 Value FANOUT AVCC * 64 ...
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... Set to 1, SYSFANOUT pin voltage output which can provide analog voltage output. (Default 1) 7.9.8 SYSTIN Target Temperature Register/ SYSFANIN Target Speed Register - Index 05h (Bank 0) Register Location: 05h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ SYSFANOUT_SEL CPUFANOUT0_SEL SYSFANOUT_Mode SYSFANOUT_Mode CPUFANOUT0_Mode CPUFANOUT0_Mode Reserved ...
Page 77
... Thermal Cruise mode or Bit 7: Reserved. Bit 6-0: CPUTIN Target Temperature. (2)When at Fan Speed Cruise mode: Bit 7-0: CPUFANIN0 Target Speed. 7.9.10 Tolerance of Target Temperature or Target Speed Register - Index 07h (Bank 0) Register Location: 07h W83627EHF/EF, W83627EHG/ Target Temperature / Target Speed Target Temperature / Target Speed ...
Page 78
... Size: 8 bits When at Thermal Cruise mode, SYSFANOUT value will decrease to this value. This register should be written a non-zero minimum stop value. W83627EHF/EF, W83627EHG/ SYSTIN Target Temperature Tolerance / SYSFANIN Target Speed Tolerance CPUTIN Target Temperature Tolerance / CPUFANIN0 Target Speed Tolerance SMARTFAN III mode: ...
Page 79
... Stop Value. 7.9.13 SYSFANOUT Start-up Value Register - Index 0Ah (Bank 0) Register Location: 0Ah Power on Default Value: 01h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ CPUFANOUT0 Stop Value mode, CPUFANOUT0 value will decrease to this - 68 - ...
Page 80
... When at Thermal Cruise mode, CPUFANOUT0 value will increase from 0 to this register value to provide a minimum value to turn on the fan. 7.9.15 SYSFANOUT Stop Time Register - Index 0Ch (Bank 0) Register Location: 0Ch Power on Default Value: 3Ch Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ SYSFANOUT Start-up Value CPUFANOUT0 Start-up Value Publication Release Date: April 7, 2009 -69- Version 1 ...
Page 81
... SMARTFAN III CPUFANOUT0 value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. W83627EHF/EF, W83627EHG/ SYSFANOUT Stop Time ...
Page 82
... The unit of this register is 0.4 second. The default time is 4 seconds. 7.9.18 Fan Output Step Up Time Register - Index 0Fh (Bank 0) Register Location: 0Fh Power on Default Value: 0Ah Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ FANOUT Value Step Down Time FANOUT Value Step Up Time Publication Release Date: April 7, 2009 -71- Version 1.94 ...
Page 83
... Set to 1, select 180 KHz. Bit 6-0: AUXFANOUT PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider W83627EHF/EF, W83627EHG/ PWM_SCALE3 PWM_CLK_SEL3 ...
Page 84
... Bit 7-2: AUXFANOUT voltage control. Bit 1-0: Reserved. OUTPUT Voltage = Note. See the Table 7.4 7.9.21 FAN Configuration Register II - Index 12h (Bank 0) Register Location: 12h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/EG Input Clock Pre_Scale Divider AUXFANOUT Value FANOUT AVCC * ...
Page 85
... Set to 1, AUXFANOUT pin voltage output which can provide analog voltage output. (Default 0) 7.9.22 AUXTIN Target Temperature Register/ AUXFANIN0 Target Speed Register - Index 13h (Bank 0) Register Location: 13h Power on Default Value: 00h W83627EHF/EF, W83627EHG/ AUXFANOUT_SEL AUXFANOUT_Mode AUXFANOUT_Mode ...
Page 86
... Read/Write Size: 8 bits (1)When at Thermal Cruise mode: Bit 3-0: Tolerance of AUXTIN Target Temperature. (2)When at Fan Speed Cruise mode: W83627EHF/EF, W83627EHG/ Target Temperature / Target Speed 1 0 AUXTIN Target Temperature Tolerance / AUXFANIN Target Speed Tolerance Reserved Publication Release Date: April 7, 2009 -75- Version 1.94 ...
Page 87
... Stop Value. 7.9.25 AUXFANOUT Start-up Value Register - Index 16h (Bank 0) Register Location: 16h Power on Default Value: 01h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ AUXFANOUT Stop Value - 76 - ...
Page 88
... The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. 7.9.27 OVT# Configuration Register - Index 18h (Bank 0) Register Location: 18h Power on Default Value: 43h W83627EHF/EF, W83627EHG/ AUXFANOUT Start-up Value ...
Page 89
... Value RAM ⎯ Index 20h- 3Fh (Bank 0) ADDRESS A6-A0 20h CPUVCORE reading 21h VIN0 reading 22h AVCC reading 23h 3VCC reading 24h VIN1 reading 25h VIN2 reading 26h VIN3 reading 27h SYSTIN temperature sensor reading W83627EHF/EF, W83627EHG/ Reserved Reserved Reserved Reserved OVT1_Mode Reserved DIS_OVT1 Reserved DESCRIPTION - 78 - ...
Page 90
... High Limit 32h 3VCC Low Limit 33h VIN1 High Limit 34h VIN1 Low Limit 35h VIN2 High Limit 36h VIN2 Low Limit 37h VIN3 High Limit 38h VIN3 Low Limit W83627EHF/EF, W83627EHG/EG DESCRIPTION Publication Release Date: April 7, 2009 -79- Version 1.94 ...
Page 91
... Low Limit of the fan speed. 3Fh CPUFANIN1 reading Note: This location stores the number of counts of the internal clock per revolution. 7.9.30 Configuration Register - Index 40h (Bank 0) Register Location: 40h Power on Default Value: 03h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/EG DESCRIPTION - 80 - ...
Page 92
... Interrupt Status Register 1 - Index 41h (Bank 0) Register Location: 41h Power on Default Value: 00h Attribute: Read Only Size: 8 bits Bit 7: A one indicates the fan count limit of CPUFANIN0 has been exceeded. W83627EHF/EF, W83627EHG/ START SMI#Enable Reserved INT_Clear Reserved Reserved Reserved INITIALIZATION 4 ...
Page 93
... Bit 2: A one indicates a High or Low limit of VIN2 has been exceeded. Bit 1: A one indicates a High or Low limit of VIN3 has been exceeded. Bit 0: A one indicates a High or Low limit of VIN1 has been exceeded. 7.9.33 SMI# Mask Register 1 - Index 43h (Bank 0) Register Location: 43h Power on Default Value: DEh W83627EHF/EF, W83627EHG/ VIN1 VIN3 ...
Page 94
... Bit 7-0: A one disables the corresponding interrupt status bit for SMI interrupt. 7.9.35 Reserved Register - Index 45h 7.9.36 SMI# Mask Register 3 - Index 46h (Bank 0) Register Location: 46h Power on Default Value: 07h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ CPUVCORE VIN0 AVCC(Pin114) 3VCC SYSTIN ...
Page 95
... Set to 0, this pin119 acts as FAN control signal and the output value of FAN control is set by this register bit 1. Bit 1: AUXFANIN1 output value if bit 0 sets to 0. Write 1, pin58(AUXFANIN1) always generates a logic high signal. Write 0, pin58 always generates a logic low signal. This bit is default 0. W83627EHF/EF, W83627EHG/ ...
Page 96
... Bit 6-0: Serial Bus address <7:1>. 7.9.39 Reserved - Index 49h (Bank 0) 7.9.40 CPUFANOUT1 with Temperature source Select - Index 4Ah (Bank 0) Register Location: 4Ah Power on Default Value: 64h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/EG 2Dh Serial Bus Addr. Reserved Reserved Reserved Reserved ...
Page 97
... ADC clock select 5.6 Khz. (22.5K/4) <5:4> ADC clock select 1.4Khz. (22.5K/16) <5:4> ADC clock select 0.35 Khz. (22.5K/64) Bit 3-2: These two bits should be set to 01h. The default value is 01h. Bit 1-0: Reserved. 7.9.42 SMI#/OVT# Control Register - Index 4Ch (Bank 0) W83627EHF/EF, W83627EHG/ Reserved ...
Page 98
... Bit 2: Over-temperature polarity. Write 1, OVT# active high. Write 0, OVT# active low. (Default 0) Bit 1-0: Reserved. 7.9.43 FAN IN/OUT Control Register - Index 4Dh (Bank 0) Register Location: 4Dh Power on Default Value: 15h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ Reserved Reserved OVTPOL DIS_OVT2 DIS_OVT3 ...
Page 99
... Set to 0, this pin113 acts as FAN control signal and the output value of FAN control is set by this register bit 1. 7.9.44 Register 50h ~ 5Fh Bank Select Register - Index 4Eh (Bank 0) Register Location: 4Eh Power on Default Value: 80h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ FANINC1 FANOPV1 FANINC2 FANOPV2 ...
Page 100
... Set to 5, select Bank5. Set to 6, select Bank6. Set to 7, select Bank7. 7.9.45 Nuvoton Vendor ID Register - Index 4Fh (Bank 0) Register Location: 4Fh Power on Default Value: <15:0> = 5CA3h Attribute: Read Only Size: 16 bits W83627EHF/EF, W83627EHG/ BANKSEL0 BANKSEL1 BANKSEL2 Reserved EN_CPUFANIN1_BP EN_AUXFANIN1_BP Reserved ...
Page 101
... Bit 4: BEEP output control for temperature SYSTIN if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 3: BEEP output control for 3VCC if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. W83627EHF/EF, W83627EHG/ VIDH ...
Page 102
... Bit 2: BEEP output control for VIN3 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. Bit 1: BEEP output control for VIN2 if the monitor value exceeds the limit value. Write 1, enable BEEP output. Write 0, disable BEEP output, which is default value. W83627EHF/EF, W83627EHG/EG 57h 4 3 ...
Page 103
... Bit 5: Diode mode selection of temperature CPUTIN if Index 5Dh bit2 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Bit 4: Diode mode selection of temperature SYSTIN if Index 5Dh bit1 is 1. Set this bit to 1, select Pentium II CPU compatible thermal diode. Bit 3-2: AUXFANIN1 Divisor bit 1:0. W83627EHF/EF, W83627EHG/ ...
Page 104
... Bit 0: Set to 1, enable battery voltage monitor. Set to 0, disable battery voltage monitor. After set this bit from the monitored value will be updated to the VBAT reading value register after one monitor cycle time. Fan divisor table: BIT 2 BIT 1 BIT 0 FAN DIVISOR W83627EHF/EF, W83627EHG/ EN_VBAT_MNT DIODES1 DIODES2 DIODES3 Reserved ...
Page 105
... Set to 1, select 180 KHz. Bit 6-0: CPUFANOUT1 PWM Pre-Scale divider. This is the divider of clock source of PWM output frequency. The maximum divider is 128 (7Fh). This divider should not be set to 0. 01h : divider is 1 02h : divider is 2 03h : divider W83627EHF/EF, W83627EHG/EG BIT 2 BIT 1 BIT 0 FAN DIVISOR 1 0 ...
Page 106
... Bit 7-2: CPUFANOUT1 voltage control. Bit 1-0: Reserved. OUTPUT Voltage = Note. See the Table 7.4 7.9.56 FAN Configuration Register III - Index 62h (Bank 0) Register Location: 62h Power on Default Value: 40h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/EG Input = Pre_Scale CPUFANOUT1 Value FANOUT AVCC * ...
Page 107
... Bit3-0: Tolerance of CPUFANIN1 Target Speed. 7.9.57 Target Temperature Register/ CPUFANIN1 Target Speed Register - Index 63h (Bank 0) Register Location: 63h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ Target Temperature Tolerance / CPUFANIN1 Target Speed Toleranc CPUFANOUT1_Mode CPUFANOUT1_Mode CPUFANOUT1_SEL Reserved TM III Mode. ...
Page 108
... Please note that Stop Value does not mean that fan really stops. It means that if the temperature keeps below low temperature limit, then the fan speed keeps on decreasing until reaching a minimam value, and this is Stop Value. 7.9.59 CPUFANOUT1 Start-up Value Register - Index 65h (Bank 0) Register Location: 65h W83627EHF/EF, W83627EHG/ Target Temperature / Target Speed TM ...
Page 109
... SMART FAN CPUFANOUT1 value is from stop value to 0. (1)When at PWM output: The unit of this register is 0.1 second. The default time is 6 seconds. (2)When at DC Voltage output: The unit of this register is 0.4 second. The default time is 24 seconds. W83627EHF/EF, W83627EHG/ CPUFANOUT1 Start-up Value 2 ...
Page 110
... This register determines the value that CPUFANOUT0 in SMART FAN increased to the next speed. 7.9.63 CPUFANOUT1 Maximum Output Value Register - Index 69h (Bank 0) Register Location: 69h Power on Default Value: FFh W83627EHF/EF, W83627EHG/ CPUFANOUT0 Max. Value CPUFANOUT0 Step Publication Release Date: April 7, 2009 ...
Page 111
... This register determines the value that CPUFANOUT1 in SMART FAN increased to the next speed. 7.9.65 CPUTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 1) Register Location: 50h Attribute: Read Only Size: 8 bits W83627EHF/EF, W83627EHG/ CPUFANOUT1 Max. Value CPUFANOUT1 Step - 100 - ...
Page 112
... Bit 7: Temperature <0> of CPUTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved. 7.9.67 CPUTIN Temperature Sensor Configuration Register - Index 52h (Bank 1) Register Location: 52h Power on Default Value: 00h Size: 8 bits Bit 7-5: Read Only - Reserved. This bit should be set to 0. W83627EHF/EF, W83627EHG/ TEMP<8:1> Reserved TEMP<0> ...
Page 113
... Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 7.9.69 CPUTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 1) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. W83627EHF/EF, W83627EHG/ THYST<8:1> Reserved THYST<0> - 102 - ...
Page 114
... Read/Write Size: 8 bits Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 7.9.72 AUXTIN Temperature Sensor Temperature (High Byte) Register - Index 50h (Bank 2) Register Location: 50h Attribute: Read Only Size: 8 bits W83627EHF/EF, W83627EHG/ TOVF<8:1> Reserved TOVF<0> Publication Release Date: April 7, 2009 -103- Version 1 ...
Page 115
... Size: 8 bits Bit 7: Temperature <0> of AUXTIN sensor, which is low byte, means 0.5 Bit 6-0: Reserved. 7.9.74 AUXTIN Temperature Sensor Configuration Register - Index 52h (Bank 2) Register Location: 52h Power on Default Value: 00h Size: 8 bits 7 6 W83627EHF/EF, W83627EHG/ TEMP<8:1> ° Reserved TEMP<0> ° ...
Page 116
... Bit 7-0: Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 7.9.76 AUXTIN Temperature Sensor Hysteresis (Low Byte) Register - Index 54h (Bank 2) Register Location: 54h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ THYST<8:1> Publication Release Date: April 7, 2009 -105- Version 1.94 ...
Page 117
... Size: 8 bits Bit 7-0: Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 7.9.78 AUXTIN Temperature Sensor Over-temperature(Low Byte) Register - Index 56h (Bank 2) Register Location: 56h Power on Default Value: 00h Attribute: Read/Write Size: 8 bits W83627EHF/EF, W83627EHG/ Reserved THYST<0> TOVF<8:1> - 106 - ...
Page 118
... Smart Fan Bit 1: A one indicates a High or Low limit of VBAT has been exceeded. Bit 0: A one indicates a High or Low limit of VSB has been exceeded. 7.9.80 SMI# Mask Register 4 - Index 51h (Bank 4) Register Location: 51h W83627EHF/EF, W83627EHG/ Reserved TOVF< ...
Page 119
... Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Bit 7-6: Reserved. Bit 5: User define BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Bit 4-2: Reserved. W83627EHF/EF, W83627EHG/ VSB VBAT Reserved Reserved TAR3 Reserved Reserved Reserved ...
Page 120
... Power on Default Value: 00h Attribute: Read/Write Size: 8 bits Bit 7-0: CPUTIN temperature offset value. The value in this register will be added to the monitored value so that the reading value will be the sum of the monitored value and the offset value. W83627EHF/EF, W83627EHG/ OFFSET<7:0> OFFSET< ...
Page 121
... Real Time Hardware Status Register I - Index 59h (Bank 4) Register Location: 59h Power on Default Value: 00h Attribute: Read Only Size: 8 bits Bit 7: CPUFANIN0 status. Read 1, the fan speed count is over the limit value. Read 0, the fan speed count is in the limit range. W83627EHF/EF, W83627EHG/ OFFSET<7:0> CPUVCORE_STS VIN0_STS ...
Page 122
... Bit 6: Smart Fan of SYSFANIN warning status. Read 1, the SYSTIN temperature has been over the target temperature for 3 minutes with full fan speed at thermal cruise mode of SmartFan 0, the temperature does not reach the warning range yet. W83627EHF/EF, W83627EHG/ ...
Page 123
... Bit 5: VIN2 Voltage status. Read 1, the voltage of VIN2 is over/under the limit value. Read 0, the voltage of VIN21 is in the limit range. Bit 4: VIN3 Voltage status. Read 1, the voltage of VIN3 is over/under the limit value. Read 0, the voltage of VIN3 is in the limit range. W83627EHF/EF, W83627EHG/ ...
Page 124
... Low Limit 56h VBAT High Limit 57h VBAT Low Limit 58h VIN4 High Limit 59h VIN4 Low Limit 5Ah Reserved 5Bh Reserved 5Ch AUXFANIN1 Fan Count Limit W83627EHF/EF, W83627EHG/EG DESCRIPTION Publication Release Date: April 7, 2009 -113 Read Version 1.94 ...
Page 125
... ADDRESS A6-A0 Note the number of counts of the internal clock for the Low Limit of the fan speed. 7.9.92 Nuvoton Test Register - Index 50h-57h (Bank 6) W83627EHF/EF, W83627EHG/EG DESCRIPTION - 114 - ...
Page 126
... FIFO THRESHOLD 1 Byte 2 Byte 8 Byte 15 Byte FIFO THRESHOLD 1 Byte W83627EHF/EF, W83627EHG/EG MAXIMUM DELAY UNTIL SERVICING AT 500K BPS Data Rate 1 x 16μs - 1.5 μs = 14.5 μ μs - 1.5 μs = 30.5 μ μs - 1.5 μs = 6.5 μ μs - 1.5 μs = 238.5 μs MAXIMUM DELAY UNTIL SERVICING AT 1M BPS Data Rate μ ...
Page 127
... The FDC monitors the bit stream that is being sent to the drive. The data patterns that require precompensation are well known, so, depending on the pattern, the bit is shifted either early or late, relative to the surrounding bits. 8.1.4 Perpendicular Recording Mode W83627EHF/EF, W83627EHG/ μs - 1.5 μs = 14.5 μ μs - 1.5 μs = 62.5 μ μs - 1.5 μs = 118.5 μs - 116 - ...
Page 128
... After the operation is completed, status information and other housekeeping information are provided to the microprocessor. The next section introduces each of the commands. 8.1.5 FDC Commands Command Symbol Descriptions: C: Cylinder Number 0 - 256 D: Data Pattern DIR: Step Direction DIR = 0: step out W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -117- Version 1.94 ...
Page 129
... NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sectors per Cylinder SK: Skip deleted data address mark SRT: Step Rate Time W83627EHF/EF, W83627EHG/EG - 118 - ...
Page 130
... N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627EHF/EF, W83627EHG/ Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 7, 2009 ...
Page 131
... N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627EHF/EF, W83627EHG/ Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution - 120 - ...
Page 132
... W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (4) Read ID W83627EHF/EF, W83627EHG/ Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
Page 133
... MFM HDS DS1 DS0 Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627EHF/EF, W83627EHG/ Command codes The first correct ID information on the cylinder is stored in the Data Register Status information after command execution Disk status after the command has been completed - 122 - ...
Page 134
... R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- -------------------- DTL/SC ------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ (6) Version PHASE R Command W83627EHF/EF, W83627EHG/ Publication Release Date: April 7, 2009 -123- REMARKS Command codes Sector ID information prior to command execution No data transfer takes place Status information after ...
Page 135
... W 0 HDS DS1 DS0 W ---------------------- C ------------------------ W ---------------------- H ------------------------ W ---------------------- R ------------------------ W ---------------------- N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627EHF/EF, W83627EHG/ 124 - REMARKS Enhanced controller REMARKS Command codes Sector ID information prior to Command execution Data transfer between the FDD and the system ...
Page 136
... N ------------------------ W -------------------- EOT ----------------------- W -------------------- GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ W83627EHF/EF, W83627EHG/ Command codes Sector ID information prior to command execution Data transfer between the FDD and the system Status information after command execution Sector ID information after command execution ...
Page 137
... Each W ---------------------- H ------------------------ Sector: W ---------------------- R ------------------------ (Repeat) W ---------------------- N ------------------------ Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- R ---------------- Undefined ------------------- (10) Recalibrate PHASE R Command W83627EHF/EF, W83627EHG/ Command codes 1 - 126 - REMARKS Command codes Bytes per Sector Sectors per Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after ...
Page 138
... DS1 DS0 Execution (11) Sense Interrupt Status PHASE R Command Result R ---------------- ST0 ------------------------- R ---------------- PCN ------------------------- (12) Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND (13) Seek PHASE R Command W83627EHF/EF, W83627EHG/ Head retracted to Track 0 Interrupt Command code 0 Status information at the end of each seek operation Command codes Command codes 1 ...
Page 139
... DS1 DS0 W -------------------- NCN ----------------------- Execution R (14) Configure PHASE R Command EIS EFIFO POLL | ------ FIFOTHR W | --------------------PRETRK ----------------------- | Execution (15) Relative Seek PHASE R Command W 1 DIR HDS DS1 DS0 W | -------------------- RCN ---------------------------- | (16) Dumpreg W83627EHF/EF, W83627EHG/ Head positioned over proper cylinder on the diskette Configure information ----| Internal registers written 128 - REMARKS ...
Page 140
... Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- R ----------------------- PCN-Drive 2-------------------- R ----------------------- PCN-Drive 3 ------------------- R --------SRT ------------------ | --------- HUT -------- R ----------- HLT -----------------------------------| ND R ------------------------ SC/EOT ---------------------- R LOCK EIS EFIFO POLL | ------ FIFOTHR -------- R -----------------------PRETRK ------------------------- (17) Perpendicular Mode PHASE R Command GAP WG W83627EHF/EF, W83627EHG/ GAP Publication Release Date: April 7, 2009 -129- REMARKS Registers placed in FIFO REMARKS Command Code ...
Page 141
... LOCK Result (19) Sense Drive Status PHASE R Command HDS DS1 DS0 Result R ---------------- ST3 ------------------------- (20) Invalid PHASE R Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- W83627EHF/EF, W83627EHG/ Command Code 0 0 LOCK Command Code Status information about the disk drive Invalid codes (no operation- FDC goes to standby state) ST0 = 80h ...
Page 142
... Along with the SB register, the SA register is used to monitor several disk-interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. RESERVED (Bit 6) STEP (Bit 5): W83627EHF/EF, W83627EHG/EG REGISTER READ SA REGISTER SB REGISTER TD REGISTER MS REGISTER DT (FIFO) REGISTER ...
Page 143
... This bit indicates the direction of head movement. 0 outward direction 1 inward direction In PS/2 Model 30 mode, the bit definitions for this register are as follows INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. W83627EHF/EF, W83627EHG/ DIR# WP INDEX HEAD# TRAK0 ...
Page 144
... Status Register B (SB Register) (Read base address + 1) Along with the SA register, the SB register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 mode, the bit definitions for this register are as follows: W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -133- ...
Page 145
... This bit indicates the complement of the WE# output pin. RESERVED (Bit 1) MOT EN A (Bit 0) This bit indicates the complement of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows W83627EHF/EF, W83627EHG/ MOT EN A Reserved WE RDATA Toggle WDATA Toggle ...
Page 146
... Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register that controls drive motors, drive selection, DRQ/IRQ enable, and FDC reset. The bit definitions are as follows: W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -135- Version 1.94 ...
Page 147
... If the three-mode FDD function is enabled (EN3MODE = 1 in LD0 CRF0, Bit 0), the bit definitions are as follows Media ID1 Media ID0 (Bit 7, 6): These two bits are read-only. These two bits reflect the value of LD0 CRF1, bits 5 and 4. W83627EHF/EF, W83627EHG/EG 1-0 2 Drive Select: 00 select drive A 01 Reserved 10 Reserved 11 Reserved ...
Page 148
... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor. 8.2.6 Data Rate Register (DR Register) (Write base address + 4) W83627EHF/EF, W83627EHG/EG TAPE SEL 0 DRIVE SELECTED ...
Page 149
... These three bits select the value of write precompensation. The following tables show the precompensation values for every combination of these bits. PRECOMP W83627EHF/EF, W83627EHG/ DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET PRECOMPENSATION DELAY 250K - 1 Mbps Default Delays 41.67 ns 83.34 ns 125.00 ns 166.67 ns 208. 138 - ...
Page 150
... In addition, data bytes pass through the data register to program or obtain results after a command. In the W83627EHF/EHG/EF/EG, this register is disabled after reset. The FIFO can enable it and change its values through the configure command. Status Register 0 (ST0) W83627EHF/EF, W83627EHG/EG PRECOMPENSATION DELAY 250K - 1 Mbps 250.00 ns ...
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... W83627EHF/EF, W83627EHG/EG Missing Address Mark. 1 When the FDC cannot detect the data address mark or the data address mark has been deleted. NW (Not Writable write Protect signal is detected from the diskette drive during execution of write data. ND (No DATA specified sector cannot be found during execution of a read, write or verifly data. ...
Page 152
... Bit 6-3: These bits are always a logic 1 during a read. DRATE1 DRATE0 (Bit 2, 1): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. W83627EHF/EF, W83627EHG/ ...
Page 153
... These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. 8.2.9 Configuration Control Register (CC Register) (Write base address + 7) This register is used to control the data rate. In PC/AT and PS/2 mode, the bit definitions are as follows: W83627EHF/EF, W83627EHG/ ...
Page 154
... This bit disables the precompensation function. It can be set by the software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC. See DR register bits 1 and 0 (Data Rate Register (DR Register) (Write base address + 4)) for how the settings correspond to individual data rates. W83627EHF/EF, W83627EHG/ ...
Page 155
... Bit 6: SSE. A logical 1 forces the Serial Output (SOUT silent state (a logical 0). Only IRTX is affected by this bit; the transmitter is not affected. Bit 5: PBFE. When PBE and PBFE of UCR are both set to logical 1, (1) if EPE is logical 1, the parity bit is fixed as logical 0 when transmitting and checking. W83627EHF/EF, W83627EHG/ ...
Page 156
... Bits 0 and 1: DLS0, DLS1. These two bits define the number of data bits that are sent or checked in each serial character. DLS1 The following table identifies the remaining UART registers. Each one is described separately in the following sections. W83627EHF/EF, W83627EHG/EG DLS0 DATA LENGTH Publication Release Date: April 7, 2009 -145- ...
Page 157
... Register (Write Only UART Control UCR Data Register Length Select Bit 0 (DLS0 Handshake HCR Data Control Terminal Register Ready (DTR) W83627EHF/EF, W83627EHG/EG Bit Number Data RX Data RX Data RX Data Bit 1 Bit 2 Bit 3 Bit 4 TX Data TX Data TX Data TX Data Bit 1 Bit 2 Bit 3 Bit 4 ...
Page 158
... Baudrate BHL Bit 8 Divisor Latch BDLAB = 1 High *: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received. **: These bits are always 0 in 16450 Mode. W83627EHF/EF, W83627EHG/EG Overrun Parity Bit No Stop Silent Error Error Bit Byte ...
Page 159
... Bit 2: PBER. This bit is set to logical 1 to indicate that the received data has the wrong parity bit. In 16550 mode, it indicates the same condition for the data on the top of the FIFO. When the CPU reads USR, it sets this bit to logical 0. W83627EHF/EF, W83627EHG/ ...
Page 160
... Bit 2: This bit is only used in the diagnostic mode. In diagnostic mode, this bit is internally connected to the modem control input RI#. Bit 1: This bit controls the RTS# output. The value of this bit is inverted and output to RTS#. Bit 0: This bit controls the DTR# output. The value of this bit is inverted and output to DTR#. W83627EHF/EF, W83627EHG/ ...
Page 161
... Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high after HSR was read by the CPU. Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU. Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read by the CPU. W83627EHF/EF, W83627EHG/ ...
Page 162
... Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits are programmed. 9.2.6 Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status. W83627EHF/EF, W83627EHG/ FIFO enable Receiver FIFO reset ...
Page 163
... Status Second RBR Data Ready Second FIFO Data Timeout Third TBR Empty W83627EHF/EF, W83627EHG/ interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled INTERRUPT SET AND FUNCTION Interrupt Source - No Interrupt pending 1. OER = 1 2. PBER =1 3. NSER = 1 4 ...
Page 164
... Bit 2: EUSRI. Set this bit to logical 1 to enable the UART status register interrupt. Bit 1: ETBREI. Set this bit to logical 1 to enable the TBR empty interrupt. Bit 0: ERDRI. Set this bit to logic 1 to enable the RBR data ready interrupt. W83627EHF/EF, W83627EHG/EG INTERRUPT SET AND FUNCTION Interrupt Source 1 ...
Page 165
... W83627EHF/EF, W83627EHG/EG 16 –1). The output frequency of DECIMAL DIVISOR 1.0 USED TO GENERATE 16X CLOCK 650 2304 975 1536 1430 1047 1478.5 857 1950 768 ...
Page 166
... Unless specified, the error percentage for all of the baud rates is 0.16%. Note: Pre-Divisor is determined by CRF0 of UART A and B. 9.2.9 User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. W83627EHF/EF, W83627EHG/EG DECIMAL DIVISOR 1.0 USED TO GENERATE 16X ...
Page 167
... W83627EHF/EHG/ EF/ 2-9 31-26, 24- Notes: n<name > : Active Low 1. Compatible Mode 2. High Speed Mode 3. For more information, please refer to the IEEE 1284 standard. W83627EHF/EF, W83627EHG/EG PIN ATTRIBUTE SPP EPP O nSTB nWrite I/O PD<0:7> PD<0:7> I nACK Intr I BUSY nWait SLCT Select O nAFD nDStrb I nERR ...
Page 168
... The following table lists the registers used in the EPP mode and identifies the bit map of the parallel port and EPP registers. Some of the registers are used in other modes as well W83627EHF/EF, W83627EHG/EG PIN NUMBER OF PIN ATTRIBUTE 36 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O ...
Page 169
... EPP Data Port 3 (R/W) Each register (or pair of registers, in some cases) is discussed below. 10.2.1 Data Port (Data Swapper) The CPU reads the contents of the printer's data latch by reading the data port. W83627EHF/EF, W83627EHG/EG Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) ...
Page 170
... EPP bus; a logical 0 means that no time-out error has occurred. Writing a logical 1 to this bit clears the time-out status bit; writing a logical 0 has no effect. 10.2.3 Printer Control Latch and Printer Control Swapper The CPU reads the contents of the printer control latch by reading the printer control swapper. The bit definitions are as follows W83627EHF/EF, W83627EHG/ ...
Page 171
... PD0-PD7 ports are read during a read operation. The leading edge of IOR# causes an EPP address read cycle to be performed and the data to be output to the host CPU. 10.2.5 EPP Data Port 0-3 These four registers are available only in EPP mode. The bit definitions for each data port are the same and as follows: W83627EHF/EF, W83627EHG/ ...
Page 172
... IOW# latches the data for the duration of the EPP write cycle. During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read cycle to be performed and the data to be output to the host CPU. W83627EHF/EF, W83627EHG/ ...
Page 173
... Second, the host performs a series of read and/or write byte operations to the selected register. Four operations are supported on the EPP: Address Write, Data Write, Address Read, and Data Read. All operations on the EPP device are performed asynchronously. W83627EHF/EF, W83627EHG/EG EPP DESCRIPTION - 162 - ...
Page 174
... EPP Version 1.7 Operation The EPP read/write cycle can start without checking whether nWait is active or inactive. Once the read/write cycle starts; however, it does not finish until nWait changes from active low to inactive high. W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -163- ...
Page 175
... EPP mode (If this option is enabled in the CRF0 to select ECP/EPP mode) 101 Reserved 110 Test mode 111 Configuration mode The mode selection bits are bits 7-5 of the Extended Control Register. 10.3.1 ECP Register and Bit Map W83627EHF/EF, W83627EHG/EG with existing parallel DESCRIPTION - 164 - ports, so the ...
Page 176
... Parallel Port Data FIFO ecpDFifo ECP Data FIFO tFifo Test FIFO cnfgA 0 0 cnfgB compress intrValue Ecr MODE Notes: W83627EHF/EF, W83627EHG/EG I/O ECP MODES R/W 000-001 Data Register R/W 011 ECP FIFO (Address) R All Status Register R/W All Control Register ...
Page 177
... Mode 011 (ECP FIFO-Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. This operation is defined only for the forward direction. The bit definitions are as follows W83627EHF/EF, W83627EHG/ ...
Page 178
... Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logical 1 during a read. 10.3.4 Device Control Register (DCR) The bit definitions are as follows W83627EHF/EF, W83627EHG/ ...
Page 179
... However, data in the tFIFO may be displayed on the parallel port data lines. 10.3.8 CNFGA (Configuration Register A) Mode = 111 This register is a read-only register. When it is read, 10h is returned indicating an 8-bit implementation. 10.3.9 CNFGB (Configuration Register B) Mode = 111 W83627EHF/EF, W83627EHG/EG - 168 - ...
Page 180
... IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are logical 1 during a read and can be written. 10.3.10 ECR (Extended Control Register) Mode = all This register controls the extended ECP parallel port functions. The bit definitions are follows: W83627EHF/EF, W83627EHG/ ...
Page 181
... Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables the interrupt generated on the falling edge of nFault. This prevents interrupts from being lost in the time between the read of the ECR and the write of the ECR. W83627EHF/EF, W83627EHG/ ...
Page 182
... NStrobe (HostClk) This pin loads data or address into the slave on its asserting edge O during write operations. This signal handshakes with Busy. PD<7:0> I/O These signals contain address, data or RLE data. W83627EHF/EF, W83627EHG/EG DESCRIPTION Publication Release Date: April 7, 2009 -171- Version 1.94 ...
Page 183
... This signal is always deasserted in ECP mode. 10.3.12 ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation necessary to initialize some of the port bits. (a) Set direction = 0, enabling the drivers. W83627EHF/EF, W83627EHG/EG DESCRIPTION acknowledge nReverseRequest. - 172 - ...
Page 184
... The W83627EHF/EHG/EF/EG hardware supports RLE decompression and can transfer compressed data to a peripheral. Odd (RLE) compression is not supported in the hardware, however. In order to transfer data in ECP mode, the compression count is written to ecpAFifo and the data byte is written to ecpDFifo. 10.3.13 FIFO Operation W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -173- Version 1.94 ...
Page 185
... The FIFO threshold is set in LD0 CRO0, bit All data transferred to or from the parallel port can proceed in DMA or Programmed I/O (non-DMA) mode, as indicated by the selected mode. The FIFO is used in Parallel Port FIFO mode or ECP Parallel Port Mode. After a reset, the FIFO is disabled. W83627EHF/EF, W83627EHG/EG - 174 - ...
Page 186
... The host must set dmaEn and serviceIntr to 0 and also must set the direction and state accordingly in the programmed I/O transfers. The ECP requests programmed I/O transfers from the host by activating the IRQ pin. The programmed I/O empties or fills the FIFO using the appropriate direction and mode. W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -175- Version 1.94 ...
Page 187
... LD5-CR60 and LD5-CR61). The keyboard controller uses the output buffer to send the scan code (from the keyboard) and required command bytes to the system. The output buffer can only be read when the output buffer full bit in the register (in the status register) is logical 1. 11.2 Input Buffer W83627EHF/EF, W83627EHG/EG P24 P25 P21 ...
Page 188
... Inhibit Switch 5 Auxiliary Device Output Buffer 6 General Purpose Time-out 7 Parity Error 11.4 Commands W83627EHF/EF, W83627EHG/EG DESCRIPTION 0: Output buffer empty 1: Output buffer full 0: Input buffer empty 1: Input buffer full This bit may be set writing to the system flag bit in the command byte of the keyboard controller ...
Page 189
... No Error Detected 01 Auxiliary Device "Clock" line is stuck low Auxiliary Device "Clock" line is stuck high 02 Auxiliary Device "Data" line is stuck low 03 04 Auxiliary Device "Data" line is stuck low AAh Self-test Returns 055h if self-test succeeds W83627EHF/EF, W83627EHG/EG FUNCTION BIT DEFINITION BIT DEFINITION - 178 - ...
Page 190
... Output next received byte of data from system to Auxiliary Device E0h Reports the status of the test inputs FXh Pulse only RC (the reset line) low for 6μs if the Command byte is even W83627EHF/EF, W83627EHG/EG FUNCTION BIT DEFINITION Publication Release Date: April 7, 2009 -179- Version 1.94 ...
Page 191
... When the KBC receives data that follows a "D1" command, the hardware control logic sets or clears GATEA20 according to received data bit 1. Similarly, the hardware control logic sets or clears KBRESET depending on received data bit 0. When the KBC receives an "FE" command, the KBRESET is pulse low for 6μs (Min.) with a 14μs (Min.) delay. W83627EHF/EF, W83627EHG/ ...
Page 192
... SGA20 (Special GATE A20 Control) 1: Drives GATE A20 signal to high. 0: Drives GATE A20 signal to low. PLKBRST# (Pull-Low KBRESET) A logical 1 on this bit causes KBRESET to drive low for 6 μS(Min.) with a 14 μS(Min.) delay. Before issuing another keyboard-reset command, the bit must be cleared. W83627EHF/EF, W83627EHG/ Res. (0) Res ...
Page 193
... UART B IRQ event Hardware Monitor IRQ event WDTO# event MIDI IRQ event RIB (UARTB Ring Indicator) event 12.1 Resume Reset Logic The RSMRST# (Pin 75) signal is a reset output and is used as the 3VSB power-on reset signal for the South Bridge. W83627EHF/EF, W83627EHG/EG Note 182 - ...
Page 194
... When the W83627EHF/EHG/EF/EG detects the 3VCC voltage rises to “V3”, it then starts a delay – “t2” before the rising edge of PWROK asserting. If the 3VCC voltage falls below “V4”, the PWROK de-asserts immediately. Timing and voltage parameters are shown in figure and table. W83627EHF/EF, W83627EHG/EG MIN. MAX. 80 130 2 ...
Page 195
... Set the delay time when rising from PWROK_LP to PWROK_ST 300 ~ 600 mS. 1: 200 ~ 300 mS. PWROK_DEL (VSB) Set the delay time when rising from PWROK_ST to PWROK. 2~1 00: No delay time. 10 W83627EHF/EF, W83627EHG/EG MIN. MAX. 300 600 2.6 2.65 2.4 2.45 DEFINITION 01: Delay 32 mS ...
Page 196
... For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2 timing is from 396(300 + 96 596(500 + 96) mS. W83627EHF/EF, W83627EHG/EG Publication Release Date: April 7, 2009 -185- Version 1.94 ...
Page 197
... IRQ/Data Frame. The host controller drives the SERIRQ signal low for clock periods. Upon a reset, the SERIRQ signal is defaulted to the Continuous mode for the host controller to initiate the first Start Frame. Please see the diagram below for more details. Start Frame Timing with source sampled a low pulse on IRQ1. W83627EHF/EF, W83627EHG/EG - 186 - ...
Page 198
... W83627EHF/EHG/EF/EG device leaves the SERIRQ tri-stated. The W83627EHF/EHG/EF/EG starts to drive the SERIRQ line from the beginning of "IRQ0 FRAME" based on the rising edge of PCICLK. The IRQ/Data Frame has a specific numeral order, as shown in Table 13.1. Table 13.1 SERIRQ Sampling Periods W83627EHF/EF, W83627EHG/EG IRQ1 FRAME IRQ0 FRAME R T ...
Page 199
... IRQ/DATA FRAME SIGNAL SAMPLED 1 IRQ0 2 IRQ1 3 SMI# 4 IRQ3 5 IRQ4 6 IRQ5 7 IRQ6 8 IRQ7 9 IRQ8 10 IRQ9 11 IRQ10 12 IRQ11 13 IRQ12 14 IRQ13 15 IRQ14 16 IRQ15 17 IOCHCK# 18 INTA# 19 INTB# 20 INTC# 21 INTD# 32:22 Unassigned W83627EHF/EF, W83627EHG/ CLOCKS PAST EMPLOYED BY START 188 - - Keyboard - UART B UART A - FDC LPT - - - - Mouse - - - - - - ...
Page 200
... IRQ15 H=Host Control R=Recovery Note: 1. There may be none, one or more Idle states during the Stop Frame. 2. The Start Frame pulse of next SERIRQ cycle may or may not start immediately after the turn-around clock of the Stop Frame. W83627EHF/EF, W83627EHG/EG IOCHCK# STOP FRAME FRAME ...