ISL54105ACRZ Intersil, ISL54105ACRZ Datasheet
ISL54105ACRZ
Specifications of ISL54105ACRZ
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ISL54105ACRZ Summary of contents
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... PART NUMBER TEMP. RANGE (°C) ISL54105ACRZ NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... QFN Package Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Supply Voltage 3.3V, pixel rate = 165MHz +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ, ...
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Electrical Specifications Specifications apply for V TMDS output load = 50Ω, TMDS output termination voltage V SYMBOL PARAMETER DIGITAL OUTPUT CHARACTERISTICS V Output HIGH Voltage 8mA Output LOW Voltage -8mA OL O POWER ...
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ISL54105A Pin Configuration RES_TERM RES_BIAS RXC- 12 RXC ...
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Pin Descriptions SYMBOL RX0-, RX0+, RX1-, RX1+, RX2-, RX2+ TMDS Inputs. Incoming TMDS data signals. RXC-, RXC+ TMDS Inputs. Incoming TMDS clock signals. TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs. TMDS output data for selected channel. TXC-, TXC+ SCL ...
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Register Listing ADDRESS REGISTER (DEFAULT VALUE) 0x00 Device ID (read only) 0x01 Channel Activity Detect (read only) 0x02 Channel Selection (0x0C) 0x03 Input Control (0x12) Recommended default: 0x63 6 ISL54105A BIT(S) FUNCTION NAME 3:0 Device Revision 1 = initial silicon, ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x04 Termination Control (0x00) 0x05 Output Options (0x00) 0x06 Data Output Drive (0x00) 0x07 Reserved (0xCC) 0x08 Equalization (0xCC) 0x09 Test Pattern Generator (0x00) 7 ISL54105A BIT(S) FUNCTION NAME 1:0 Reserved Set to ...
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Register Listing (Continued) ADDRESS REGISTER (DEFAULT VALUE) 0x0A PRBS7 Error Counter Link 0 (read only) 0x0B PRBS7 Error Counter Link 1 (read only) 0x0C PRBS7 Error Counter Link 2 (read only) 0x10 PLL Bandwidth (0x10) Recommended default: 0x12 8 ISL54105A ...
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Application Information The ISL54105A is a TMDS regenerator, locking to the incoming DVI or HDMI signal with triple Clock Data Recovery units (CDRs) and a Phase Locked Loop (PLL). The PLL generates a low jitter pixel clock from the incoming ...
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Next, a 15m DualLink DVI cable was attached and terminated into a female TPA2 adapter and the eye captured in Figure 4. FIGURE 4. CHROMA EYE DIAGRAM AFTER 15m CABLE The eye is not meeting the minimum requirements of either ...
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TMDS receiver it is attached to. 3. (41, 53) V _ESD D Tx ISL54105A FIGURE 8. ISL54105A ESD PROTECTION DIODES This is non-ideal and can cause the ISL54105A to fail HDMI Compliance ...
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PCB Layout Recommendations Because of the high speed of the TMDS signals, careful PCB layout is critical to maximize performance. The following guidelines should be adhered to as closely as possible: • All TMDS pair traces should have a characteristic ...
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ISL54105A Serial Communication Overview The ISL54105A uses a 2-wire serial bus for communication with its host. SCL is the Serial Clock line, driven by the host and SDA is the Serial Data line, which can be driven by all devices ...
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SCL SDA FIGURE 16. VALID DATA CHANGES ON THE SDA BUS START Command ISL54105A Serial Bus ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 (Repeat if desired) STOP Command S T Serial Bus ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L72.10x10B 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (PUNCH QFN) Rev 0, 5/07 10.00 9. PIN 1 INDEX AREA (4X) 0.15 TOP VIEW PACKAGE OUTLINE 4.70 10.00 TYPICAL RECOMMENDED LAND PATTERN 11° ±1° ALL ...