NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 154

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DMA Status/Interrupt Enable register
1 4 2
D M A c h a n n e l r e g i s t e r s
Address: FF90 0014 / 34 / 54 / 74 / 94 / B4 / D4 / F4 / 114 / 134 / 154 / 174 / 194 / 1B4 / 1D4 / 1F4
The interrupt enable (IE) bits can be set to cause an interrupt to occur when the
corresponding interrupt status bit is set in the DMA Status register. The interrupt
pending (IP) bits are set to indicate begin active. These bits are cleared by writing a
1 to the same bit locations.
Register bit assignment
Table 51: DMA Status/Interrupt Enable register bit definition
D31
D30
Bits
NCIP
Rsvd
15
31
ECIP
30
14
R/C
R/C
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
NRIP
29
13
CAIP
28
12
NCIP
ECIP
Mnemonic
PCIP
27
11
26
10
Reserved
0
0
Reset
25
9
PCIE
24
8
Normal completion interrupt pending
Set when a buffer descriptor has been closed (for normal
conditions) and either the NCIE bit is set or the IDONE bit
is active in the current buffer descriptor. A normal DMA
channel completion occurs when the BLEN count expires
(gets to 0) or when a peripheral device signals completion.
Error completion interrupt pending
Set when the DMA channel encounters either a bad buffer
descriptor pointer or a bad data buffer pointer. When ECIP
is set, the DMA channel stops until the bit is cleared by
firmware; the DMA channel does not go to the next buffer
descriptor.
When ECIP is cleared, the buffer descriptor is tried again
from where it left off. The CA bit in the DMA Control
register can be used to abort the current buffer descriptor
and go to the next descriptor.
Description
NCIE
23
7
BLEN
ECIE
22
6
NRIE
21
5
CAIE
20
4
WRAP IDONE
19
3
18
2
LAST
17
1
FULL
16
0