NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 183

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 58: Ethernet Transmit Status register bit definition
D09
D08
D07
Bits
R
R
N/A
Access
TXAUR
TXAJ
Not used
Mnemonic
0
0
N/A
Reset
Transmit aborted — underrun
Set to 1 to indicate that the last Ethernet packet was not
transmitted successfully; packet transmission was aborted
due to a FIFO underrun condition. A FIFO underrun
condition indicates that the DMA controller was unable to
fill the FIFO at a fast enough rate compared to the rate of
transmission on the Ethernet medium, for one of these
reasons:
When this bit is set, the transmit frame is flushed
automatically from the transmit FIFO. TXREGE and
TXFIFOH in the Ethernet General Status register become
active when the FIFO is ready to start receiving the next
packet.
TXBC in the Ethernet General Status register becomes
active when TXAUR is set.
Transmit abort — jumbo
Set to 1 to indicate that the last Ethernet packet was not
transmitted successfully; packet transmission was aborted
due to a jumbo condition. A jumbo condition means that the
packet was too large; that is, greater than 1518 bytes.
Packets larger than 1518 bytes are not transmitted
successfully unless the HUGEN bit is set in the MAC
Configuration register.
When this bit is set, the transmit frame is automatically
flushed from the transmit FIFO. TXREGE and TXFIFOH
in the Ethernet General Status register become active when
the FIFO is ready to start receiving the next packet.
TXBC in the Ethernet General Status register becomes
active when TXAJ is set.
Always set to 0.
Description
w w w . d i g i e m b e d d e d . c o m
The memory peripheral device was not configured for
bursting.
the Ethernet interface.
The DMA controller was not configured for bursting.
The memory peripheral device is too slow to support
E t h e r n e t M o d u l e
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