BD8153EFV-E2 Rohm Semiconductor, BD8153EFV-E2 Datasheet - Page 11

• Manufacturer Part Number: BD8153EFV-E2
• Description: IC POWER SUP VARI 4CH HTSSOP-B24
• Manufacturer: Rohm Semiconductor
• Series: -r

Specifications of BD8153EFV-E2

• Applications: TFT-LCD Monitors
• Current - Supply: 2mA
• Voltage - Supply: 2.1 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

© 2009 ROHM Co., Ltd. All rights reserved.
BD8153EFV
www.rohm.com
(7) Design of the Feedback Resistor Constant
(8) Positive-side Charge Pump Settings
(9) Negative-side Charge Pump Settings
Refer to the following equation to set the feedback resistor. As the setting range, 10 k to 330 k is recommended. If
the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset
voltage becomes larger by the input bias current 0.4 µA(Typ.) in the internal error amplifier.
BU8513EFV incorporates a charge pump controller, thus making it possible to generate stable gate voltage.
The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended. If the
resistor is set lower than a 10k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage
becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp.
In order to prevent output voltage overshooting, add capacitor C8 in parallel with R8. The recommended capacitance is
1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate.
By connecting capacitance to the DLS, a rising delay time can be set for the positive-side charge pump.
The delay time is determined by the following formula.
BU8513EFV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate
voltage. The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended.
If the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset
voltage becomes larger by the input bias current 0.4 µA (Typ.) in the internal error amp.
The delay time is internally fixed at 200 us.
In order to prevent output voltage overshooting, insert capacitor C6 in parallel with R6. The recommended capacitance
is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate.
 Delay time of charge pump block t
Vo =
Vo =
Vo3 =
t
where, C
DELAY
R8 + R9
R8 + R9
= ( C
R9
R9
DLS
-
DLS
is the external capacitance.
R6
R7
 1.24
 0.6 )/5 µA [s6]
 1.24
 1.04 + 0.2 V
[V]
[V]
DELAY
[V]
11/17
Sep-up
1000 pF to 4700 pF
Vo
1000 pF to 4700 pF
R8
R9
C8
Vo2
7
Fig. 35
FB1
R8
R9
C6
Reference voltage 1.24 V
Fig. 36
Vo3
＋
－
ERR
R6
R7
12
FB2
Technical Note
2009.07 - Rev.B
Reference voltage 1.24 V
＋
－
Fig.37
23
24
ERR
REF
FB3
0.2 V
－
＋
ERR
1.24 V