AD7869JR Analog Devices Inc, AD7869JR Datasheet - Page 5

• Manufacturer Part Number: AD7869JR
• Description: IC I/O PORT 14BIT ANLG 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7869JR

• Rohs Status: RoHS non-compliant
• Applications: Analog I/O
• Interface: TTL/CMOS
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 28-SOIC (7.5mm Width)
• Mounting Type: Surface Mount
• Converter Type: ADC/DAC
• Resolution: 14b
• Data Rate: 0.083MSPS
• Digital Interface Type: Serial
• Pin Count: 28
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

DIP Pin
Number
POWER SUPPLY
7 & 23
10 & 22
8 & 19
6 & 17
ANALOG SIGNAL AND REFERENCE
21
9
20
11
12
ADC INTERFACE AND CONTROL
2
3
4
5
1
24
DAC INTERFACE AND CONTROL
14
15
16
13
18
REV. A
Mnemonic
V
V
AGND
DGND
V
V
RO ADC
RO DAC
RI DAC
CLK
RFS
RCLK
DR
CONVST
CONTROL
TFS
DT
TCLK
LDAC
NC
DD
SS
IN
OUT
CONVST
RO DAC
RI DAC
DGND
AGND
RCLK
V
CLK
RFS
V
V
OUT
DR
DD
SS
10
11
12
1
2
3
4
5
6
7
8
9
Function
Positive Power Supply, 5 V
Negative Power Supply, –5 V
Analog Ground. Both AGND pins must be tied together.
Digital Ground. Both DGND pins must be tied together.
ADC Analog Input. The ADC input range is 3 V.
Analog Output Voltage from DAC. This output comes from a buffer amplifier. The range is bipolar, 3 V
with RI DAC = +3 V.
Voltage Reference Output. The internal ADC 3 V reference is provided at this pin. This output may be used as a
reference for the DAC by connecting it to the RI DAC input. The external load capability of this reference is 500 A.
DAC Voltage Reference Output. This is one of two internal voltage references. To operate the DAC with this
internal reference, RO DAC should be connected to RI DAC. The external load capability of the reference is 500 A.
DAC Voltage Reference Input. The voltage reference for the DAC must be applied to this pin. It is internally
buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7869 is 3 V.
Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to V
enables the internal laser-trimmed oscillator.
Receive Frame Synchronization, Logic Output. This is an active low open-drain output that provides a framing
pulse for serial data. An external 4.7 k pull-up resistor is required on RFS.
Receive Clock, Logic Output. RCLK is the gated serial clock output that is derived from the internal or external
ADC clock. If the CONTROL input is at V
the RCLK output is gated off (three-state) after serial transmission is complete. RCLK is an open-drain output and
requires an external 2 k pull-up resistor.
Receive Data, Logic Output. This is an open-drain data output used in conjunction with RFS and RCLK to transmit
data from the ADC. Serial data is valid on the falling edge of RCLK when RFS is low. An external 4.7 k resistor is
required on the DR output.
Convert Start, Logic Input. A low to high transition on this input puts the track-and-hold amplifier into the hold
mode and starts an ADC conversion. This input is asynchronous to the CLK input.
Control, Logic Input. With this pin at 0 V, the RCLK is noncontinuous. With this pin at –5 V, the RCLK is contin-
uous. Note, tying this pin to V
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for the DAC with serial
data expected after the falling edge of this signal.
Transmit Data, Logic Input. This is the data input that is used in conjunction with TFS and TCLK to transfer
serial data to the input latch.
Transmit Clock, Logic Input. Serial data bits are latched on the falling edge of TCLK when TFS is low.
Load DAC, Logic Input. A new word is transferred into the DAC latch from the input latch on the falling edge
of this signal.
No Connect.
NC = NO CONNECT
(Not to Scale)
AD7869
TOP VIEW
DIP
24
23
22
21
20
19
18
17
16
15
14
13
CONTROL
V
V
V
RO ADC
AGND
NC
DGND
TCLK
DT
TFS
LDAC
DD
SS
IN
AD7869 PIN FUNCTION DESCRIPTION
5%. Both V
PIN CONFIGURATIONS
DD
5%. Both V
places the part in a factory test mode where normal operation is not exhibited.
DD
–5–
SS
SS
pins must be tied together.
, the clock runs continuously. With the CONTROL input at DGND,
pins must be tied together.
0.299 (7.6)
0.291 (7.39)
0.01 (0.254)
0.006 (0.15)
1. LEAD NO. 1 INDENTIFIED BY A DOT.
2. SOIC LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS.
28
1
(1.27)
BSC
0.05
0.708 (18.02)
0.696 (17.67)
0.019 (0.49)
0.014 (0.35)
SOIC
15
14
0.096 (2.44)
0.089 (2.26)
0.414 (10.52)
0.398 (10.10)
0.013 (0.32)
0.009 (0.23)
6
0
0.03 (0.76)
0.02 (0.51)
x 45
0.042 (1.067)
0.018 (0.457)
AD7869
SS