S29GL256S10TFI010 Spansion Inc., S29GL256S10TFI010 Datasheet

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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29GL_128S_01GS_00 ® ™ Eclipse Flash (128 Mbyte) (64 Mbyte) (32 Mbyte) (16 Mbyte) ™ Notice On Data Sheet Designations Revision 01 ® ...

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... Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” ...

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... Publication Number S29GL_128S_01GS_00 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. ...

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Buffer Programming (512-bytes) Sector Erase (128 kbytes) Active Read at 5 MHz Typical Program and Erase Rates Maximum Current Consumption ...

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... Error Types and Clearing Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.6 Embedded Algorithm Performance Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6. Software Interface Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.1 Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.2 Device ID and Common Flash Interface (ID-CFI) ASO Map . . . . . . . . . . . . . . . . . . . . . . . . . 60 Hardware Interface 7. Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1 Address and Data Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 Input/Output Summary 7.3 Versatile I/O Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7 ...

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AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Figures Figure 1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Tables Table 1.1 S29GL-S Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table 10.6 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... Max The GL-S family combines the best features of eXecute In Place (XIP) and Data Storage flash memories. This family has the fast random access of XIP flash along with the high density and fast program speed of Data Storage flash. Read access to any random location takes 120 ns depending on device density and I/O power supply voltage ...

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... The host system writes command codes to the flash device address space. The EAC receives the commands, performs all the necessary steps to complete the command, and provides status information during the progress of an EA. ...

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... ECC Status: provides the status of any error detection or correction action taken when reading the selected Page. The main Flash Memory Array is the primary and default address space but, it may be overlaid by one other address space, at any one time. Each alternate address space is called an Address Space Overlay (ASO). ...

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... When an Embedded Algorithm is suspended, the Data Polling ASO is visible until the device has suspended the EA. When the EA is suspended the Data Polling ASO is exited and Flash Array data is available. The Data Polling ASO is reentered when the suspended EA is resumed, until the EA is again suspended or finished ...

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... Autoselect (ID) or CFI overlay will cause the now combined ID-CFI address map to appear. The ID-CFI address map appears within, and overlays the Flash Array data of, the sector selected by the address used in the ID-CFI enter command. While the ID-CFI ASO is entered the content of all other sectors is undefined ...

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... Common Flash Memory Interface The JEDEC Common Flash Interface (CFI) specification (JESD68.01) defines a standardized data structure that may be read from a flash memory device, which allows vendor-specified software algorithms to be used for entire families of devices. The data structure contains information for system configuration such as various electrical and timing parameters, and special functions supported by the device ...

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... Persistent Protection Bits (PPB) ASO The PPB ASO contains one bit of a Flash Memory Array for each Sector in the device. When the PPB ASO is entered, the PPB bit for a sector appears in the Least Significant Bit (LSB) of each word in the sector. ...

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... DYB. The sector may be protected by other features of ASP. 2.7 ECC Status ASO The ECC Status ASO displays the status of any error correction action taken when reading a Page of the main flash array. A single word of status is displayed at word location 0 of each Page. February 11, 2011 S29GL_128S_01GS_00_01 ( ® ...

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... Secure Silicon Region (OTP) The Secure Silicon Region (SSR) provides an extra flash memory area that can be programmed once and permanently protected from further changes One Time Program (OTP) area. The SSR is 1024 bytes in length. It consists of 512 bytes for Factory Locked Secure Silicon Region and 512 bytes for Customer Locked Secure Silicon Region ...

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... Sector Highest Address Sector. Every main flash array sector has a non-volatile (PPB) and a volatile (DYB) protection bit associated with it. When either bit is 0, the sector is protected from program and erase operations. The PPB bits are protected from program and erase when the PPB Lock bit is 0. There are two methods for managing the state of the PPB Lock bit, Persistent Protection and Password Protection ...

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... Persistent Protection Bits (PPB) The Persistent Protection Bits (PPB) are located in a separate nonvolatile flash array. One of the PPB bits is assigned to each sector. When a PPB is 0 its related sector is protected from program and erase operations. The PPB are programmed individually but must be erased as a group, similar to the way individual words may be programmed in the main array but an entire sector must be erased at the same time ...

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3.4.6 Sector Protection States Summary Each sector can be in one of the following protection states:  Unlocked – The sector is unprotected and protection can be changed by a simple ...

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If both lock bits are selected to be programmed at the same time, the operation will abort. Once the Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is permanently disabled and no changes to the protection scheme ...

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 The Password Unlock command cannot be accepted any faster than once every 100 µs ± 20 µs. This makes it take an unreasonably long time (58 million years) for a ...

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Read Operations 4.1 Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self- timed with the same latency from CE# or address to valid data (t 4.2 Page ...

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... Program and Erase Summary Flash data bits are erased in parallel in a large group called a sector. The Erase operation places each data bit in the sector in the logical 1 state (High). Flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state. A data bit of 0 cannot be programmed back succeeding read shows that the data is still 0 ...

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A program operation may be suspended to allow reading of another location (not in the Line being programmed).  No other program or erase operation may be started during a suspended program operation - program or erase commands will ...

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... Page is erased and reprogrammed. The Word Programming command always disables ECC on the Page programmed. Thus, incremental bit or word programming (bit-walking) is allowed but has the effect of disabling the flash device internal error correction capability on the Page where incremental programming is done. ...

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... Next, the system writes the number of word locations minus 1. This tells the device how many write buffer addresses are loaded with data and therefore when to expect the Program Buffer to flash confirm command. The Sector Address must match in the Write to Buffer command and the Write Word Count command ...

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... Load a Word Count value greater than the buffer size (255).  Write an address that is outside the Line provided in the Write to Buffer command.  The Program Buffer to Flash command is not issued after the Write Word Count number of data words is loaded. When any of the conditions that cause an abort of write buffer command occur the abort will happen immediately after the offending condition, and will indicate a Program Fail in the Status Register at bit location 4 (PSB = 1) due to Write Buffer Abort bit location 3 (WBASB = 1) ...

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... Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data Yes ABORT Write to Buffer Operation? No Write next Address/Data pair (Note Write Program Buffer to Flash Confirm, Sector Address Read DQ7-DQ0 with Addr = LAST LOADED ADDRESS DQ7 = Data DQ5 = 1? DQ1 = 1? Yes Yes Read DQ7-DQ0 with ...

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... Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data Yes Yes ABORT Write to Buffer Operation? No Write next Address/Data pair (Note Write Program Buffer to Flash Confirm, Sector Address Read Status Register Yes DRB SR[ Yes PSB SR[ Program Fail Yes WBASB SR[ ...

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Sequence Issue Unlock Command 1 Issue Unlock Command 2 Issue Write to Buffer Command at Sector Address Issue Number of Locations at Sector Address Example words to pgm words to ...

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... Chip Erase The chip erase function erases the entire main Flash Memory Array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all 0 data pattern prior to electrical erase. After a successful chip erase, all locations within the device contain FFFFh ...

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The system can determine the status of the erase operation by reading the Status Register or using Data Polling. Refer to Status Register on page 38 on page 40 for more information. Once the sector erase operation has begun, the ...

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... The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. This command is valid only during sector erase or program operation. The Erase Suspend command is ignored if written during the chip erase operation. ...

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... ASO Exit. The following source code example of using the CFI Entry and Exit functions. Refer to the Spansion Low Level Driver User's Guide (available on www.spansion.com) for general information on Spansion flash memory software development guidelines. /* Example: CFI Entry command */ *( (UINT16 *)base_addr + 0x55 ) = 0x0098; /* write CFI entry command */ /* Example: CFI Exit command */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0 ...

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5.3.6.6 PPB ASO The system can access the PPB ASO by issuing the PPB entry command sequence during Read Mode. This entry command does not use a sector address from the ...

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... Status Monitoring There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the methods called Data Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the S29GL-S family. One additional method is reading the Status Register. Only the Status Register method will be supported in future technology nodes ...

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Bit # 15:8 Bit Reserved Description Bit Name Reset X Status Busy Status Invalid Ready X Status Notes: 1. Bits 15 thru 8, and 0 are reserved for future use and ...

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Data Polling Status During an active Embedded Algorithm the EAC switches to the Data Polling ASO to display EA status to any read access. A single word of status information is aliased in all locations of the device address ...

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Note: 1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 5.4.3.2 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an ...

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DQ2: Toggle Bit II Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II ...

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... When a timeout occurs, the software must send a reset command to clear the timeout bit (DQ5) and to return the EAC to read array mode. In this case possible that the flash will continue to communicate busy for µs after the reset command is sent. February 11, 2011 S29GL_128S_01GS_00_01 ...

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... If an erase was suspended before the error the device returns to the erase suspended state awaiting flash array read or a command write.  Otherwise, the device will be in standby state awaiting flash array read or a command write. 5.5.1 Embedded Operation Error If an error occurs during an embedded operation (program, erase, blank check, or password unlock) the device (EAC) remains busy ...

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... When the busy period ends the device returns to normal operation, the data polling status is no longer overlaid, RY/BY# is High, and the status register shows ready with valid status bits. The device is ready for flash array read or write of a new command. February 11, 2011 S29GL_128S_01GS_00_01 ...

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After the protection error status busy period the Status Register will show the following:  SR[ Valid status displayed  SR[ May or may not be erase suspended after the protection error busy period  SR[5] ...

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– Reads the status register and returns to WBA busy state  Write Buffer Abort Reset command  Status Register Clear command 5.6 Embedded Algorithm Performance Table Parameter Sector Erase Time ...

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Command State Transitions Command Current State Read and Condition Address RA Data RD - READ READ Read Protect = False READSR - (return) Table 5.8 Read Unlock Command State Transition Status Command Current Register and Read State Read Condition ...

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Table 5.10 Erase Suspend State Command Transition Command and Current State Condition Address Data ESR (1) - SR( SR( ESSR - Note: 1. State will automatically ...

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Table 5.13 Erase Suspend - Program Command State Transition Current State Command Read and Condition Address RA Data RD WC > 256 or SA ≠ SA ES_WB ES_WB WC ≤ 256 and < Write ...

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... Status Register Status Register Read Read Enter Clear RA x555h x555h RD x70h x71h PSR PGSR (PSR PSSR (PS) PS (return ® GL-S MirrorBit Family Program Erase Program Buffer to Suspend Suspend flash Enhanced Enhanced (confirm) Method (2) Method (SA) x29h xB0h x51h - - - - - - PSR (PG) PSR (PG NOT a valid “Write-to-Buffer-Abort Reset” Command ...

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Table 5.18 Lock Register State Command Transition Command Current State and Read Condition Address RA Data LRPG1 - LRPG1 LRPG - LRPG LRSR - (return) LREXT - LREXT Command and Current State Condition Address Data CFI ...

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Table 5.22 Secure Silicon Sector Program State Command Transition Command and Current State Condition Address Data SSRPG1 - WC > 256 or SA ≠ SA SSR_WB WC ≤ 256 and SA ...

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Table 5.24 Non-Volatile Protection Command State Transition Command Software Current and Read Reset / State Condition ASO Exit Address RA xh Data RD 00F0h PPB - PPB READ PPBPG1 - PPBPG1 READ SR( PPBPG PPBPG SR(7) = ...

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Current State Command Transition BLCK Table 5.9 CER Table 5.9 CFI Table 5.19 CFISR Table 5.19 DYB Table 5.26 DYBEXT Table 5.26 DYBSET Table 5.26 DYBSR Table 5.26 ER Table 5.9 ...

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Current State Command Transition PPBPG1 Table 5.24 PPBSR Table 5.24 PPD Table 5.23 PPEXT Table 5.23 PPPG Table 5.23 PPPG1 Table 5.23 PPSR Table 5.23 PS Table 5.17 PSR Table 5.17 PSSR Table 5.17 PPWB25 Table 5.23 READ Table 5.7 ...

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... XXX RD Reset/ASO Exit 1 XXX F0 (Notes 7, 16) SSR Entry 3 555 AA Read (Note Word Program 4 555 AA Write to Buffer 6 555 AA Program Buffer to Flash (confirm) Write-to-Buffer-Abort 3 555 AA Reset (Note 11) SSR Exit (Note 11) 4 555 AA Reset/ASO Exit 1 XXX F0 (Notes 7, 16) February 11, 2011 S29GL_128S_01GS_00_01 ( Table 6.1 Command Definitions (Sheet ...

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... XXX (Notes 12, 16) Reset/ASO Exit 1 XXX (Notes 7, 16) SSR Entry 3 555 Read (Note Word Program 4 555 Write to Buffer 6 555 Program Buffer to Flash 1 SA (confirm) Write-to-Buffer-Abort 3 555 Reset (Note 11) SSR Exit (Note 11) 4 555 Reset/ASO Exit 1 XXX (Notes 7, 16) Lock Register Entry 3 ...

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Command Sequence First (Note 1) Addr Data Global Non-Volatile Sector Protection Freeze Command Set Definitions PPB Lock Entry 3 555 AA PPB Lock Bit Cleared 2 XXX A0 PPB Lock Status ...

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... Device ID and Common Flash Interface (ID-CFI) ASO Map The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic feature set information for the device. ...

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Description Lower Software Bits Upper Software Bits Device ID Device ID Word Address (SA) + 0010h (SA) + 0011h (SA) + 0012h (SA) + 0013h (SA) + 0014h (SA) + 0015h ...

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... Gb) 001Ah (512 Mb) N Device Size = 2 byte; 0019h (256 Mb) 0018h (128 Mb) 0001h Flash Device Interface Description 0 = x8-only x16-only x8/x16 capable 0000h 0009h Max. number of byte in multi-byte write = 2 (00 = not supported) 0000h Number of Erase Block Regions within device 0001h 1 = Uniform Device Boot Device ...

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... D7-D4: Volt D3-D0: 100 mV WP# Protection 00h = Flash device without WP Protect (No Boot) 01h = Eight 8 kB Sectors at TOP and Bottom with WP (Dual Boot) 02h = Bottom Boot Device with WP Protect (Bottom Boot) 0004h (Bottom) 03h = Top Boot Device with WP Protect (Top Boot) ...

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Table 6.6 CFI Primary Vendor-Specific Extended Query (Sheet Word Address (SA) + 0078h (SA) + 0079h Data Embedded Hardware ...

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Hardware Interface 7. Signal Descriptions 7.1 Address and Data Configuration Address and data are connected in parallel (ADP) via separate signal inputs and I/Os. 7.2 Input/Output Summary Symbol RESET# Input CE# ...

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RESET#. Since RY/BY open drain output, several RY/BY# pins can be tied together in parallel with a pull up resistor the output is Low (Busy), the device is actively erasing, programming, or ...

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... Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. 8.1 Interface States Table 8.1 describes the required value of each interface signal for each interface state. Interface State Power-Off with Hardware ...

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Power Conservation Modes 8.3.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and ...

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the Write state. If CE# returns High, the interface goes to the Standby state. Back to Back accesses, in which CE# remains Low between accesses, requires an address change to ...

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Electrical Specifications 9.1 Absolute Maximum Ratings Storage Temperature Plastic Packages Ambient Temperature with Power Applied Voltage with Respect to Ground All pins (Note 1) Output Short Circuit Current Notes: 1. Minimum DC voltage on input ...

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Symbol V V Power Supply level below which re-initialization is required LKO and V RST and V VCS CC t Duration ...

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Input Signal Overshoot Figure 9.3 Maximum Negative Overshoot Waveform max IL V min IL – ...

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9.4 DC Characteristics Parameter Description I Input Load Current LI I Output Leakage Current Active Read Current CC1 Intra-Page Read Current CC2 CC V Active ...

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Capacitance Characteristics Parameter Symbol OUT C IN2 Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A Parameter Symbol OUT C IN2 Notes: 1. Sampled, not ...

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10. Timing Specifications 10.1 Key to Switching Waveforms Waveform 10.2 AC Test Conditions Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output ...

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Power On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the V device in a system should have the V the package connections (this capacitor is generally on the order of 0.1 ...

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10.3.2 Hardware (Warm) Reset During Hardware Reset (t When RESET# continues to be held at V held but not Cold Reset has not ...

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AC Characteristics 10.4.1 Asynchronous Read Operations Parameter JEDEC Std t t Read Cycle Time AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV CE t Page Access Time PACC t ...

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Amax-A0 CE# OE# DQ15-DQ0 Amax-A0 CE# OE# DQ15-DQ0 Note: Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access. Amax-A4 A3-A0 ...

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Asynchronous Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t OEPH t t GHWL GHWL t t ELWL ...

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Amax-A0 CE# OE# WE# DQ15-DQ0 Amax-A0 CE# OE# WE# DQ15-DQ0 February 11, 2011 S29GL_128S_01GS_00_01 ( ...

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Amax-A0 CE# OE# WE# DQ15-D0 Amax-A0 CE# OE# WE# DQ15- Figure 10.10 Write to Read (t ) Operation Timing Diagram CE tAH ...

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Figure 10.12 Read to Write (CE# Toggle) Operation Timing Diagram Amax-A0 CE# OE# WE# DQ15-A0 Parameter JEDEC Std t t WHWH1 WHWH1 t t WHWH2 WHWH2 t BUSY t SR/W t ...

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Addresses CE# OE# WE# Data RY/BY# Note program address program data, D Addresses CE# OE# WE# Data RY/BY# Note sector address (for sector erase valid address for reading status data. ...

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Figure 10.15 Data# Polling Timing Diagram (During Embedded Algorithms) Addresses CE OE# t WE# DQ7 DQ6–DQ0 t BUSY RY/BY# Note Valid address. Illustration shows first status ...

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Alternate CE# Controlled Write Operations Parameter JEDEC Std t t AVAV AVWL AS t ASO t t WLAX AH t AHT t t DVWH WHDX DH t CEPH t 0EPH t t GHEK ...

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Amax-A0 CE# OE# WE# DQ15-D0 February 11, 2011 S29GL_128S_01GS_00_01 ( Figure 10.19 ...

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Physical Interface 11.1 56-Pin TSOP 11.1.1 Connection Diagram Notes: 1. Pin 28, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Spansion for test or other purposes and ...

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11.1.2 Physical Diagram Figure 11.2 56-Pin Thin Small Outline Package (TSOP PACKAGE TS 56 JEDEC MO-142 (B) EC SYMBOL MIN. A --- A1 0.05 A2 0.95 b1 ...

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FBGA 11.2.1 Connection Diagram A13 WE# 4 RY/BY Notes: 1. Ball E1, Do Not Use (DNU), a device internal signal is connected to the package ...

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11.2.2 Physical Diagram Figure 11.4 LAE064—64-ball Fortified Ball Grid Array (FBGA PACKAGE LAE 064 JEDEC N/A 9. 9.00 mm PACKAGE SYMBOL MIN NOM A --- ...

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... Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. ...

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... Package Type D = Fortified Ball-Grid Array Package (LAE064 Thin Small Outline Package (TSOP) Standard Pinout W = Wafer with KGD test flow Speed Option 100 110 120 ns Option, 1024, 512, 256, 128 Megabit Page-Mode Flash Memory, IO ® GL-S MirrorBit Family and V Range 2.7 to 3.6V, highest address sector protected ...

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Valid Combinations The Recommended Combinations table lists configurations planned to be available in volume. The table below will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on ...

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... 13. Other Resources Visit www.spansion.com 13.1 Links to Software Downloads and related information on flash device support is available at http://www.spansion.com/Support/Pages/DriversSoftware.aspx  Spansion low-level drivers  Enhanced flash drivers  Flash file system Downloads and related information on simulation modeling and CAD modeling support is available at http://www.spansion.com/Support/Pages/SimulationModels.aspx  ...

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Revision History Section Revision 01 (February 11, 2011) Initial release Description ® GL-S MirrorBit Family ...

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... Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2011 Spansion Inc. All rights reserved. Spansion and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ...