SI4709-B-GM Silicon Laboratories Inc, SI4709-B-GM Datasheet - Page 16

• Manufacturer Part Number: SI4709-B-GM
• Description: IC FM RADIO TUNER 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI4709-B-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si4708/09-B
4.7. Reference Clock
The Si4708/09-B accepts a 32.768 kHz reference clock
to the RCLK pin. The reference clock is required
whenever the ENABLE bit is set high. Refer to Table 3,
“DC Characteristics
voltage
Characteristics," on page 10 for frequency tolerance
information.
4.8. Control Interface
Two-wire slave-transceiver and three-wire interfaces
are provided for the controller IC to read and write the
control registers. Refer to “4.9. Reset, Powerup, and
Powerdown” for a description of bus mode selection.
Registers may be written and read when the V
is applied regardless of the state of the V
supplies. RCLK is not required for proper register
operation.
4.8.1. 3-Wire Control Interface
For three-wire operation, a transfer begins when the
SEN pin is sampled low by the device on a rising SCLK
edge. The control word is latched internally on rising
SCLK edges and is nine bits in length, comprised of a
four bit chip address A7:A4 = 0110b, a read/write bit
(write = 0 and read = 1), and a four bit register address,
A3:A0. The ordering of the control word is A7:A5, R/W,
A4:A0. Refer to Section 5. "Register Summary" on page
19 for a list of all registers and their addresses.
For write operations, the serial control word is followed
by a 16-bit data word and is latched internally on rising
SCLK edges.
For read operations, a bus turn-around of half a cycle is
followed by a 16-bit data word shifted out on rising
SCLK edges and is clocked into the system controller
on falling SCLK edges. The transfer ends on the rising
SCLK edge after SEN is set high. Note that 26 SCLK
cycles are required for a transfer, however, SCLK may
run continuously.
For details on timing specifications and diagrams, refer
to Table 5, “3-Wire Control Interface Characteristics,” on
page 7, Figure 2, “3-Wire Control Interface Write Timing
Parameters,” on page 7, and Figure 3, “3-Wire Control
Interface Read Timing Parameters,” on page 7.
4.8.2. 2-Wire Control Interface
For two-wire operation, the SCLK and SDIO pins
function in open-drain mode (pull-down only) and must
be pulled up by an external device. A transfer begins
with the START condition (falling edge of SDIO while
SCLK is high). The control word is latched internally on
rising SCLK edges and is eight bits in length, comprised
of a seven bit device address equal to 0010000b and a
read/write bit (write = 0 and read = 1).
16
levels
1
and
,” on page 5 for input switching
Table 7,
"FM
IO
Receiver
Confidential Rev. 1.4
D
supply
or V
A
The device acknowledges the address by driving SDIO
low after the next falling SCLK edge, for 1 cycle. For
write operations, the device acknowledge is followed by
an eight bit data word latched internally on rising edges
of SCLK. The device acknowledges each byte of data
written by driving SDIO low after the next falling SCLK
edge, for 1 cycle. An internal address counter
automatically increments to allow continuous data byte
writes, starting with the upper byte of register 02h,
followed by the lower byte of register 02h, and onward
until the lower byte of the last register is reached. The
internal address counter then automatically wraps
around to the upper byte of register 00h and proceeds
from there until continuous writes end. Data transfer
ends with the STOP condition (rising edge of SDIO
while SCLK is high). After every STOP condition, the
internal address counter is reset.
For read operations, the device acknowledge is
followed by an eight bit data word shifted out on falling
SCLK edges. An internal address counter automatically
increments to allow continuous data byte reads, starting
with the upper byte of register 0Ah, followed by the
lower byte of register 0Ah, and onward until the lower
byte of the last register is reached. The internal address
counter then automatically wraps around to the upper
byte of register 00h and proceeds from there until
continuous reads cease. After each byte of data is read,
the controller IC must drive an acknowledge (SDIO = 0)
if an additional byte of data will be requested. Data
transfer ends with the STOP condition. After every
STOP condition, the internal address counter is reset.
For details on timing specifications and diagrams, refer
to
Characteristics
Control Interface Read and Write Timing Parameters,”
on page 9 and Figure 5, “2-Wire Control Interface Read
and Write Timing Diagram,” on page 9.
4.9. Reset, Powerup, and Powerdown
Driving the RST pin low will disable the Si4708/09 and
its control bus interface, and reset the registers to their
default settings. Driving the RST pin high will bring the
device out of reset. As the part is brought out of reset,
the SEN pin is used to select between 2-wire and 3-wire
control interface operation.
Table 6,
1,2,3
,” on page 8, Figure 4, “2-Wire
“2-Wire
Control
Interface