SI4709-B-GM Silicon Laboratories Inc, SI4709-B-GM Datasheet - Page 17

• Manufacturer Part Number: SI4709-B-GM
• Description: IC FM RADIO TUNER 20-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: -r

Specifications of SI4709-B-GM

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The bus mode selection method requires the use of the
SEN pin. To select 2-wire operation, the SEN pin must
be sampled high by the device on the rising edge of
RST. To select 3-wire operation, the SEN pin must be
sampled low by the device on the rising edge of RST.
When proper voltages are applied to the Si4708/09, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE =
DISABLE = 0. Setting ENABLE = 1 and DISABLE = 0
puts the device in powerup mode. To power down the
device, disable RDS (Si4709 only), set Reg4(5:4),
Reg4(3:2), and Reg4(1:0) to 0b10. then write 1 to the
ENABLE and DISABLE bits. After being written to 1,
both bits will get cleared as part of the internal device
powerdown sequence. To put the device back into
powerup mode, set ENABLE = 1 and DISABLE = 0 as
described above. The ENABLE bit should never be
written to a 0.
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x V
ESD diodes from clamping to the V
response to the output swing of the other device. The
bias point is set with a 370 k resistor to V
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
Note: All parameters applied on rising edge of RST.
Table 8. Selecting 2-Wire or 3-Wire Control
IO
on the LOUT and ROUT pins to prevent the
Interface Busmode Operation
Bus Mode
3-wire
2-wire
1,2
,” on page 10, regardless of
IO
IO
is supplied. In
or GND rail in
IO
SEN
and GND.
0
1
Confidential Rev. 1.4
4.11. Initialization Sequence
Refer to Figure 8, “Initialization Sequence,” on page 18.
To initialize the device:
1. Supply V
2. Supply V
3. Select 2-wire or 3-wire control interface bus mode
4. Provide RCLK. Steps 3 and 4 may be reversed when
5. Set the ENABLE bit high and the DISABLE bit low to
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc
2. Set the ENABLE bit high and the DISABLE bit high
3. (Optional) Remove RCLK.
4. Remove V
To power up the device (after power down):
1. Note that V
2. (Optional) Set the AHIZEN bit low to disable the dc
3. Supply V
4. Provide RCLK. Steps 3 and 4 may be reversed when
5. Set the ENABLE bit high and the DISABLE bit low to
steps 1 and 2 may be reversed. Power supplies may
be sequenced in any order.
operation as described in Section 4.9. "Reset,
Powerup, and Powerdown" on page 16.
using an external oscillator.
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics
with normal part operation.
bias of 0.5 x V
while in powerdown, but preserve the states of the
other bits in Register 07h. Note that in powerup the
LOUT and ROUT pins are set to the common mode
voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
to place the device in powerdown mode. Note that all
register states are maintained so long as V
supplied and the RST pin is high.
not supplied, refer to device initialization procedure
above.
bias of 0.5 x V
but preserve the states of the other bits in Register
07h. Note that in powerup the LOUT and ROUT pins
are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of
AHIZEN.
using an external oscillator.
powerup the device. Software should wait for the
powerup time (as specified by Table 7, “FM Receiver
Characteristics
with normal part operation.
A
A
IO
A
and V
and V
IO
while keeping the RST pin low. Note that
and V
is still supplied in this scenario. If V
IO
IO
1,2
1,2
D
D
volts at the LOUT and ROUT pins
volts at the LOUT and ROUT pins,
,” on page 10) before continuing
,” on page 10) before continuing
.
.
D
supplies as needed.
Si4708/09-B
IO
is
IO
is
17