VRS51C1000-40-QG-ISPV2 Ramtron, VRS51C1000-40-QG-ISPV2 Datasheet - Page 12

• Manufacturer Part Number: VRS51C1000-40-QG-ISPV2
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-QG-ISPV2

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 10 mm
• Lead Free Status / Rohs Status: Details

Power Control Register
The VRS51C1000 provides two power saving modes,
Idle and Power Down, which are controlled by the
PDOWN and IDLE bits of the PCON register at
address 87h.
T
In Idle mode, the processor is stopped but the oscillator
continues to run. The content of the SRAM, I/O state
and SFR registers are maintained and the Timer and
external interrupts are left operational. The processor
will be woken up when an external event, triggering an
interrupt, occurs.
In Power Down mode, the oscillator and peripherals
are disabled. The contents of the SRAM and the SFR
registers, however, are maintained. The only way to
exit from the Power Down mode is via a hardware
Reset (note that the Watchdog Timer is stopped in
Power Down).
When the VRS51C1000 is in power down, its current
consumption drops to about 150uA.
The SMOD bit of the PCON register controls the
oscillator divisor applied to the Timer 1 when used as a
baud rate generator for the UART. Setting this bit to 1
doubles the UART’s baud rate generator frequency.
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ABLE
Bit
7
6
5
4
3
2
1
0
VRS51C1000
7
17: P
Mnemonic
SMOD
GF1
GF0
PDOWN
IDLE
OWER
6
C
ONTROL
5
Unused
R
Description
1: Double the baud rate of the serial port
frequency that was generated by Timer 1.
0: Normal serial port baud rate generated by
Timer 1.
General Purpose Flag
General Purpose Flag
Power down mode control bit
Idle mode control bit
EGISTER
4
(PCON) - SFR 87
3
2
H
RAMS1
1
RAMS0
0
Input/Output Ports
The VRS51C1000 has 36 bi-directional lines grouped
into four 8-bit I/O ports and one 4-bit I/O port. These
I/Os can be individually configured as input or output.
Except for the P0 I/Os, which are of the open drain
type, each I/O is made of a transistor connected to
ground and a weak pull-up resistor (transistor based).
Writing a 0 in a given I/O port bit register will activate
the transistor connected to VSS, this will bring the I/O
to a LOW level.
Writing a 1 into a given I/O port bit register de-activates
the transistor between the pin and ground. In this case
an internal weak pull-up resistor will bring the pin to a
HIGH level (except for Port 0 which is open-drain).
To use a given I/O as an input, a 1 must be written into
its associated port register bit. By default, upon reset
all I/Os are configured as inputs.
I/O ports are not designed to source current.
Structure of the P1, P2, P3 and P4 Ports
The following figure provides the general structure of
the P1, P2 and P3 port I/Os. For these ports, the
output stage is composed of a transistor (X1) and a
transistor set configured as a weak pull-up. Note that
the figure below does not show the intermediary logic
that connects the output of the register and the output
stage together because this logic varies with the
auxiliary function of each port.
F
Each I/O may be used independently as a logical
input or output. When used as an input, as mentioned
in previously, the corresponding bit register must be
high. This corresponds to #Q=0 in the above figure.
IGURE
Internal Bus
Write to
Register
Read Register
6: G
Read Pin
ENERAL
S
TRUCTURE OF THE
D Flip-Flop
O
UTPUT
Q
Q
S
TAGE OF
page 12 of 48
P1, P2, P3
The VRS51C1000
Vcc
X1
Pull-up
Network
AND
P4
IC Pin