VRS51C1000-40-QG Ramtron, VRS51C1000-40-QG Datasheet - Page 23

• Manufacturer Part Number: VRS51C1000-40-QG
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-QG

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFP-44
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 10 mm
• Lead Free Status / Rohs Status: Details

UART Operation in Mode 1
In Mode 1 operation, 10 bits are transmitted (through
TXD) or received (through RXD). The transactions are
composed of: a Start bit (Low); 8 data bits (LSB first)
and one Stop bit (high). The reception is completed
once the Stop bit sets the RB8 flag in the SCON
register. Either Timer 1 or Timer 2 controls the baud
rate in this mode.
The following diagram shows the serial port structure
when configured in Mode 1.
______________________________________________________________________________________________
www.ramtron.com
F
SMOD
IGURE
RCLK
Timer 1
Overflow
VRS51C1000
÷2
0 1
17: S
Write to
0
0
SBUF
Timer 2
Overflow
1
1
RXD
ERIAL
TCLK
1-0 Transition
Detector
P
ORT
÷16
1
M
S
D
ODE
CLK
Start
Detector
LOAD SBUF
Start
TX Clock
÷16
Bit
1
Q
AND
RX Clock
3 B
ZERO DETECTOR
TX Control Unit
LOCK
RX Control Unit
Internal Bus
TI
RI
Internal Bus
D
SBUF
SBUF
IAGRAM
9-Bit Shift Register
Shift
Serial Port
Interrupt
Shift
Send
Data
SBUF
SHIFT
READ SBUF
Load
TXD
UART Transmission in Mode 1
Transmission in this mode is initiated by any
instruction that makes use of SBUF as a destination
register. The 9
is loaded by the “write to SBUF” signal. This event also
flags/informs the TX Control Unit that a transmission
has been requested.
It is after the next rollover in the divide-by-16 counter
when transmission actually begins. It follows that the
bit times are synchronized to the divide-by-16 counter
and not to the “write to SBUF” signal.
When a transmission begins, it places the start bit at
TXD. Data transmission is activated one bit time later.
This activation enables the output bit of the transmit
shift register to TXD. One bit time after that, the first
shift pulse occurs.
In this Mode, zeros are clocked in from the left as data
bits are shifted out to the right. When the most
significant bit of the data byte is at the output position
of the shift register, the 1 that was initially loaded into
the 9
all positions to the left of that contain zeros. This
condition flags the TX Control Unit to shift one more
time.
UART Reception in Mode 1
A one to zero transition at pin RXD will initiate
reception. It is for this reason that RXD is sampled at a
rate of 16 multiplied by the baud rate that has been
established. When a transition is detected, 1FFh is
written into the input shift register and the divide-by-16
counter is immediately reset. The divide-by-16 counter
is reset in order to align its rollovers with the
boundaries of the incoming bit times.
In total, there are 16 states in the counter. During the
7
detector samples the value of RXD. The accepted
value is the value that was seen in at least two of the
three samples. The purpose of doing this is for noise
rejection. If the value accepted during the first bit time
is not zero, the receive circuits are reset and the unit
goes back to searching for another one to zero
transition. All false start bits are rejected by doing this.
If the start bit is valid, it is shifted into the input shift
register, and the reception of the rest of the frame will
proceed.
For a receive operation, the data bits come in from the
right as 1’s shift out on the left. As soon as the start bit
arrives at the leftmost position in the shift register, (9-
th
, 8
th
th
position is to the immediate left of the MSB, and
and 9
th
th
counter states of each bit time; the bit
bit position of the transmit shift register
page 23 of 48