ZLF645E0P2032G Zilog, ZLF645E0P2032G Datasheet - Page 138

• Manufacturer Part Number: ZLF645E0P2032G
• Description: Microcontrollers (MCU) 32K Flash 1K RAM 20 pin
• Manufacturer: Zilog

Specifications of ZLF645E0P2032G

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 1 KB
• Interface Type: ICP, UART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP-20
• Minimum Operating Temperature: 0 C
• Lead Free Status / Rohs Status: Details

PS026407-0408
Crystal 1 Oscillator Pin (XTAL1)
Crystal 2 Oscillator Pin (XTAL2)
Internal Clock Signals (SCLK and TCLK)
Zilog
stray capacitance of the PCB or the crystal is high, the loading capacitance C1 and C2
must be reduced further to ensure stable oscillation before the T
5-6 ms. For more details, see
For Stop Mode Recovery operation, bit 5 of SMR register allows you to select the Stop
Mode Recovery delay, which is the T
MCU executes instruction immediately after it wakes up from the STOP mode. If
resonator or crystal is used as a clock source then STOP mode recovery delay needs to be
selected (Bit 5 of SMR = 1).
For both resonator and crystal oscillator, the oscillation ground must go directly to the
ground pin of the microcontroller. The oscillation ground must use the shortest distance
from the microcontroller ground pin and it must be isolated from other connections.
The Crystal 1 Oscillator time-based input pin connects a parallel-resonant crystal or
ceramic resonator to the on-chip oscillator input. Additionally, an optional external single-
phase clock can be connected to the on-chip oscillator input.
The Crystal 2 Oscillator time-based output pin connects a parallel-resonant crystal or
ceramic resonant to the on-chip oscillator output.
The CPU and internal peripherals are driven by the internal SCLK signal during normal
execution. During HALT mode, the interrupt logic is driven by the internal TCLK signal.
The frequency of these signals with respect to the XTAL1 clock input is selectable either
by programming bit 2 of the Flash’s User Option Byte 1 for no division of the XTAL1
signal input, dividing it by a factor of two, and optionally by applying an additional
divide-by-16 prescaler enabled through SMR register bit 0 (see
displayed in
during normal operation and HALT mode. The prescaler is disabled by a POR or Stop
Mode Recovery.
®
recommends not to use more than 10 pF loading capacitor for the crystal. If the
Figure
42. Selecting the divide-by-16 prescaler reduces device power draw-
Table 82
POR
on page 164.).
. If Stop Mode Recovery delay is not selected, the
ZLF645 Series Flash MCUs
Crystal 1 Oscillator Pin (XTAL1)
POR
Table 70 on page
Product Specification
(POR time is typically
141), as
130