DS1990A-F5 Maxim Integrated Products, DS1990A-F5 Datasheet
DS1990A-F5
Specifications of DS1990A-F5
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DS1990A-F5 Summary of contents
Page 1
... Latched by its Flange, or Locked with a Ring Pressed Onto its Rim § Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus: Approved Under Entity Concept for use in Class I, Division 1, Group and D Locations ORDERING INFORMATION â 16.25 DS1990A-F5 DS1990A-F3 01 â 17.35 EXAMPLES OF ACCESSORIES â DS9096P DS9101 DS9093RA ...
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... PHYSICAL SPECIFICATION Size Weight DS1990A Safety ABSOLUTE MAXIMUM RATINGS IO Voltage to GND IO Sink Current Junction Temperature Storage Temperature Range Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... IO 64-BIT LASERED ROM Each DS1990A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 2 for details. The 1- Wire CRC is generated using a polynomial generator consisting of a Shift and XOR gates as shown in Figure 3. ...
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... X 1-Wire BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1990A is a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire communication signals can be generated under software control using a single port pin. Alternatively, the DS2480B 1-Wire line driver chip or serial port adapters based on this chip (DS9097U series) can be used ...
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... All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS1990A is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ...
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... DS1990A contains only the 64-bit ROM without any additional data fields, Match ROM and Skip ROM are not applicable. The DS1990A will remain silent (inactive) upon receiving a ROM function command that it doesn't support. This allows the DS1990A to coexist on a multidrop bus with other 1-Wire devices that do respond to Match ROM or Skip ROM (example DS1990A and DS1994). ...
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... The initialization sequence required to begin any communication with the DS1990A is shown in Figure 6. A Reset Pulse followed by a Presence Pulse indicates the DS1990A is ready to receive a ROM function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t edge. Figure 6. INITIALIZATION PROCEDURE “ ...
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... During the t RL data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS1990A will not hold the data line low at all, and the voltage starts rising as soon over. ...