DS1990A-F5 Maxim Integrated Products, DS1990A-F5 Datasheet - Page 3

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DS1990A-F5

Manufacturer Part Number
DS1990A-F5
Description
Serial Number Registration
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1990A-F5

Lead Free Status / Rohs Status
No

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Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
DESCRIPTION
The diagram in Figure 1 shows the major function blocks of the device. The DS1990A takes the energy it needs to
operate from the IO line, as indicated by the Parasite Power block. The ROM Function Control units includes the 1-
Wire interface and the logic to implement the ROM function commands, which access 64 bits of lasered ROM.
Figure 1. DS1990A BLOCK DIAGRAM
64-BIT LASERED ROM
Each DS1990A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 2 for details. The 1-
Wire CRC is generated using a polynomial generator consisting of a Shift and XOR gates as shown in Figure 3.
The polynomial is X
available in Application Note 27.
The Shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8
48
CRC returns the Shift register to all 0s.
th
bit of the serial number has been entered, the Shift register contains the CRC value. Shifting in the 8 bits of
System requirement.
Full Rpup range guaranteed by design and simulation, not production tested. Production testing performed at a fixed Rpup value.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded
systems, an active pullup such as that found in the DS2480 may be required.
Capacitance on the IO pin could be 800pF when power is first applied. If a 5kW  r esistor is used to pull up the IO line to V
after power has been applied the parasite capacitance will not affect normal communications.
Input load is to ground.
The voltage on IO needs to be less or equal to V
conditions, V
All voltages are referenced to ground.
V
V
30nC per 72 time slots at 5.0V pullup voltage with a 5kW pullup resistor and t
The reset low time (t
conceal interrupt pulses if this device is used in parallel with a DS1994.
An additional reset or communication sequence cannot begin until the reset high time has expired.
e represents the time required for the pullup circuitry to pull the voltage on IO up from V
d represents the time required for the pullup circuitry to pull the voltage on IO up from V
master.
Presence pulse is guaranteed only after a preceding Reset Pulse (
Guaranteed by design, simulation only. Not production tested.
IH
PUP
is a function of the internal supply voltage.
= external pullup voltage.
8
ILMAX
+ X
IO
may have to be reduced to as much as 0.5V to always guarantee a Presence Pulse.
5
RSTL
+ X
th
) should be restricted to a maximum of 960 µs, to allow interrupt signaling; a longer duration could mask or
bit of the family code has been entered, then the serial number is entered. After the
4
+ 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is
Function Control
ROM
ILMAX
whenever the master drives the line low. Under certain low voltage
3 of 8
t
RSTL
Parasite Power
).
SLOT
Lasered ROM
£ 120µs.
64-bit
IL
IL
to V
to the input-high threshold of the bus
IH
.
PUP
, 5µs

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