A8296SESTR-T Allegro Microsystems Inc, A8296SESTR-T Datasheet - Page 16

• Manufacturer Part Number: A8296SESTR-T
• Description: IC REG LNB SGL SUPPLY 16-QFN
• Manufacturer: Allegro Microsystems Inc

Specifications of A8296SESTR-T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A8296
Status Registers
The main fault conditions: undervoltage lockout (UVLO), over-
current (OCP), and thermal shutdown (TSD) are all indicated by
setting the relevant bits in the Status register. In all fault cases,
after the bit is set, it remains latched until the I
has successfully read the A8296, assuming the fault has been
resolved.
The undervoltage lockout (UVLO) bit indicates either the input
voltage at the VIN pin is too low or the A8296 internal supply
voltage (VREG) is too low.
The Disable bit (DIS) indicates the status of the LNB output.
The DIS is set when either a fault occurs (UVLO, OCP, TSD, or
CPOK) or when the LNB output is turned off using the Enable
bit (ENB) via the I
Table 4. Status Register Bit Descriptions
Bit
0
1
2
3
4
5
6
7
Table 3. Status Register Description and IRQ Operation
Bit
0
1
2
3
4
5
6
7
TRIMS
CPOK
Name
UVLO
PNG
OCP
TSD
2
DIS
C™ interface. The DIS bit is latched and is
–
(I
2
TRIMS
CPOK
Name
UVLO
C™-Compatible Read Register)
OCP
PNG
TSD
DIS
–
The DIS bit is set to 1 when the A8296 is disabled, (ENB = 0) or there is a fault: UVLO, OCP, CPOK, or TSD.
If this bit is set low, the internal charge pump is not operating correctly (VCP). If the charge pump voltage is
too low, the LNB output is disabled and the DIS bit is set.
This bit will be set to a 1 if the LNB output current exceeds the overcurrent threshold (I
the overcurrent disable time (t
Factory use only.
Set to 1 when the A8296 is enabled and the LNB output voltage is either too low or too high (nominally ±9%
from the LNB DAC setting). Set to 0 when the A8296 is enabled and the LNB voltage is within the acceptable
range (nominally ±5% from the LNB DAC setting).
Not used.
The TSD bit is set to 1 if the A8296 has detected an overtemperature condition. If the TSD bit is set to 1, then
the DIS bit is also set to 1.
The UVLO bit is set to 1 if either the voltage at the VIN pin or the voltage at the VREG pin is too low. If the
UVLO bit is set to 1, then the DIS bit is also set to 1.
Single LNB Supply and Control Voltage Regulator
LNB output disabled
Charge pump OK
Overcurrent
Trim bits locked
Power Not Good
Not used
Thermal shutdown
VIN or VREG undervoltage
Function
2
C™ master
DIS
). If the OCP bit is set to 1, then the DIS bit is also set to 1.
Latched?
Yes
Yes
Yes
Yes
Yes
No
No
–
only reset when there are no faults and the A8296 output is turned
back on using the Enable (ENB) bit via the I
The Power Not Good (PNG) and Charge Pump OK (CPOK) bits
are set based on the conditions sensed at the LNB output and
VCP pins, respectively. These bits are not latched and, unlike
the other fault bits, may become reset without an I
sequence. The PNG and CPOK bits are continuously updated.
There are three methods to detect when the Status register
changes: responding to the interrupt request (IRQ) pin going low,
continuously polling the Status register via the I
detecting a fault condition external to the A8296 and performing
a diagnostic poll of the A8296. In any case, the master should
read and re-read the Status register until the status changes.
Description
LNB enabled and no faults
V
I
None
LNB voltage within range
I
I
2
2
2
CP
C™ read and fault removed
C™ read and fault removed
C™ read and fault removed
> V
Reset Condition
BOOST
+ 5V
–
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
OUT(MAX)
Effect on IRQ Pin
IRQ set low
IRQ set low
IRQ set low
None
None
None
None
–
) for more than
2
C™ interface.
2
C™ interface, or
2
C™ read
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