M25P16-VMN3TPB Micron Technology Inc, M25P16-VMN3TPB Datasheet - Page 22

• Manufacturer Part Number: M25P16-VMN3TPB
• Manufacturer: Micron Technology Inc

Specifications of M25P16-VMN3TPB

• Lead Free Status / Rohs Status: Compliant

6.4.4
22/59
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to ‘1’, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
S
C
D
Q
sequence
0
High Impedance
1
2
Instruction
3
4
5
6
7
MSB
7
8
6
Status Register Out
9 10 11 12 13 14 15
5
4
3
2
1
0
MSB
7
6
Status Register Out
5
4
3
2
1
0
7
AI02031E