NOII4SM6600A-QDC ON Semiconductor, NOII4SM6600A-QDC Datasheet - Page 24

• Manufacturer Part Number: NOII4SM6600A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOII4SM6600A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pixel Output Timing
Using Two Analog Outputs
The pixel signal at the OUT1 (OUT2) output becomes valid after
four SYS_CLOCK cycles when the internal X_SYNC (equal to
start of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time (see
T2: 4 SYS_CLOCK cycles.
Table 13
Figure 19. Pixel Output Timing using Two Analog Outputs
on page 20)
Figure 18. Basic Frame and Line Timing
Rev. 9 | www.onsemi.com | Page 24 of 32
Figure
19). The
Multiplexing to One Analog Output
The pixel signal at the OUT1 output becomes valid after five
SYS_CLOCK cycles when the internal X_SYNC (equal to start
of PIXEL_VALID output) appears (see
PIXEL_VALID and EOL/EOF pulses can be delayed by the user
through the DELAY register.
T1: Row blanking time
T2: 5 SYS_CLOCK cycles.
NOII4SM6600A
Figure
20). The