LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 143
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP20C-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 8-1. sysIO Banking
V
Each bank has a separate V
such as LVTTL, LVCMOS, and PCI. LVTTL, LVCMOS3.3, LVCMOS2.5 and LVCMOS1.2 also have fixed threshold
options allowing them to be placed in any bank. The VCCIO voltage applied to the bank determines the ratioed
input standards that can be supported in that bank. It is also used to power the differential output drivers.
V
In addition to the bank V
that powers the differential and referenced input buffers. V
headroom to satisfy the common-mode range requirements of these drivers and input buffers.
V
The JTAG pins have a separate V
mines the electrical characteristics of the LVCMOS JTAG pins, both the output high level and the input threshold.
Input Reference Voltage (V
Each bank can support up to two separate V
old for the referenced input buffers. The location of these V
can be used as regular I/Os if the bank does not require a V
V
When interfacing to DDR memory, the V
input from the memory. A voltage divider between V
CCIO
CCAUX
CCJ
REF1
(1.2V/1.5V/1.8V/2.5V/3.3V)
(1.2V/1.5V/1.8V/2.5V/3.3V)
for DDR Memory Interface
(3.3V)
CCIO
V
V
V
V
GND
V
V
GND
REF1(7)
REF2(7)
CCIO7
CCIO6
REF2(6)
REF1(6)
CCIO
supplies, devices have a V
supply that powers the single-ended output drivers and the ratioed input buffers
REF1,
CCJ
power supply that is independent of the bank V
V
REF1
REF2
REF
input must be used as the reference voltage for the DQS and DQ
Bank 0
Bank 5
)
input voltages, V
REF1
8-3
CC
and GND is used to generate an on-chip reference volt-
CCAUX
REF
core logic power supply, and a V
REF
Bank 1
Bank 4
pins is pre-determined within the bank. These pins
voltage.
is required because V
REF1
and V
LatticeECP/EC and LatticeXP
REF2
, that are used to set the thresh-
V
V
V
V
V
V
GND
GND
REF1(2)
REF2(2)
REF2(3)
REF1(3)
CCIO2
CCIO3
CCIO
CC
sysIO Usage Guide
does not have enough
CCAUX
supplies. V
auxiliary supply
CCJ
deter-
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