LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 390
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP20C-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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PCB Layout Recommendations
Lattice Semiconductor
for BGA Packages
reflow process. This is due to the surface tension of the solder and flux in its molten state pulling each ball into the
center of the pad.
Figure 14-14. Misalignment of BGA Balls vs. QPF Leads
Controlling the oven re-flow profile is one of the most important assembly parameters for consistent and reliable
BGA placement. Profiles are typically tested on a pre-run. One or two panels are run to dial in the process, then
visual and X-ray inspection equipment are used for verification.
BGA packages present numerous benefits previously unobtainable in surface mount packaging technology. BGAs
provide higher pin counts in a much smaller area than was previous possible. No longer is the package design lim-
ited to connections along the periphery on the outside quadrants of the package edge like a PQFP or TQFP out-
line. Fully populated ball grid arrays with pitches as small as 0.4 mm are available.
Some BGA devices are arranged with de-populated interconnect near or around the center. These are dependent
on the die size and number of pins. The area void of interconnect in the middle of the array has some advantages,
it can be used for escape routing vias or tying directly to the ground or power planes.
Although the packages can be quite complex and densely populated, all of these packages receive strict quality
and reliability testing and are widely accepted today by designers and PCB fabrication/assembly houses. All of this
is due to advances in equipment and technology that have allowed a smooth transition into the assembly flow.
BGA Package Test and Assembly
How can a pad/ball/pin be tested that can’t be seen? All connections are hidden under the substrate at the ball
interconnect, making it impossible to directly probe or test. To address this limitation, Lattice programmable devices
provide JTAG, BSCAN, and boundary scan cells that allow electronic test and continuity of each pin with a bound-
ary scan tester. This can be embedded into the system itself or driven externally from a high-speed test head. The
boundary scan can test the pins or board for simple continuity tests or full functional test by shifting in test patterns
through the JTAG port.
For debug or prototype boards it may be necessary to place test points, open vias, or pads to have access to a
given set of pins in order to drive, over-drive or observe a given set of signals. These can be very small, as many
14-15
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