LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 171
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number:
LFXP20C-5F484C
Manufacturer:
Lattice Semiconductor Corporation
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Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-6. Generating Pseudo Dual Port RAM (RAM_DP) Module Customization – Configuration Tab
Users can specify the Address Depth and Data width for the Read Port and the Write Port in the text boxes pro-
vided. In this example we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs of
different port widths in the case of Pseudo Dual Port and True Dual Port RAMs.
The check box Enable Output Registers inserts the output registers in the Read Data Port, as the output registers
are optional for the EBR-based RAMs.
The Reset Mode can be selected to be Asynchronous Reset or Synchronous Reset. GSR or Global Set Reset can
be checked to be Enabled or Disabled.
The Input Data and the Address Control is always registered, as the hardware only supports synchronous opera-
tion for the EBR based RAMs
Users can also pre-initialize their memory with the contents they specify in the Memory file. It is optional to provide
this file in the RAMs. However, in the case of ROM, it is required to provide the Memory file. These files can be of
Binary, Hex or Addresses Hex format. The details of these formats are discussed in the Initialization File section of
this technical note.
At this point, users can click the Generate button to generate the module that they have customized. A netlist in the
desired format is then generated and placed in the specified location. Users can incorporate this netlist in their
designs.
Users can check the Import LPC to ispLEVER project check box to automatically import the file in the Project Nav-
igator.
Once the Module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in the top level
module of their design.
The various memory modules, both EBR and Distributed, are discussed in detail later in this document.
9-6
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