WJLXT972ALC.A4 S E001 Intel, WJLXT972ALC.A4 S E001 Datasheet - Page 50

• Manufacturer Part Number: WJLXT972ALC.A4 S E001
• Manufacturer: Intel

Specifications of WJLXT972ALC.A4 S E001

• Lead Free Status / Rohs Status: Compliant

Intel
5.7.3.2
50
Caution:
®
LXT972A Single-Port 10/100 Mbps PHY Transceiver
Note:
Physical Medium Attachment Sublayer
5.7.3.2.1
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive
idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link.
In 100 Mbps mode, link is established when the descrambler becomes locked and remains locked
for approximately 50 ms. Link remains up unless the descrambler receives less than 16 consecutive
idle symbols in any 2 ms period. This operation filters out small noise hits that may disrupt the link.
For short periods, MLT-3 idle waveforms meet all criteria for 10BASE-T start delimiters. A
working 10BASE-T receive may temporarily indicate link to 100BASE-TX waveforms. However,
the PHY does not bring up a permanent 10 Mbps link.
The LXT972A Transceiver reports link failure through the MII status bits (Register bits 1.2 and
17.10) and interrupt functions. Link failure causes the LXT972A Transceiver to re-negotiate if
auto-negotiation is enabled.
5.7.3.2.2
The LXT972A Transceiver normally transmits data packets only if it detects the link is up. Setting
Register bit 16.14 = 1 overrides this function, allowing the LXT972A Transceiver to transmit data
packets even when the link is down. This feature is provided as a transmit diagnostic tool.
Auto-negotiation must be disabled to transmit data packets in the absence of link. If auto-
negotiation is enabled, the LXT972A Transceiver automatically transmits FLP bursts if the link is
down.
During normal operation, Intel does not recommend setting Register bit 16.14 for 100 Mbps
receive functions because receive errors may be generated.
5.7.3.2.3
For 100BASE-TX links, a start-of-stream delimiter (SSD) or /J/K symbol pair causes assertion of
carrier sense (CRS). An end-of-stream delimiter (ESD) or /T/R symbol pair causes de-assertion of
CRS. The PMA layer also de-asserts CRS if IDLE symbols are received without /T/R. However, in
this case RX_ER is asserted for one clock cycle when CRS is de-asserted.
Intel does not recommend using CRS for Interframe Gap (IFG) timing for the following reasons:
5.7.3.2.4
The LXT972A Transceiver asserts RX_DV to indicate that the received data maps to valid
symbols. In 100 Mbps operation, RX_DV is active with the first nibble of preamble.
•
•
CRS de-assertion time is slightly longer than CRS assertion time. As a result, an IFG interval
appears somewhat shorter to the MAC than it actually is on the wire.
CRS de-assertion is not aligned with TX_EN de-assertion on transmit loopbacks in half-
duplex mode.
Link
Link Failure Override
Carrier Sense
Receive Data Valid
Document Number: 249186-004
Revision Date: 25-Oct-2005
Datasheet