JL82575EB S LAAK Intel, JL82575EB S LAAK Datasheet - Page 2

• Manufacturer Part Number: JL82575EB S LAAK
• Manufacturer: Intel

Specifications of JL82575EB S LAAK

• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Compliant

On-Board Management Features
The Intel 82575EB Gigabit Ethernet Controller enables network
manageability implementations required by IT personnel for remote
control and alerting (IPMI, KVM Redirection, Media Redirection) by
sharing the LAN port and providing standard interfaces to a Board
Management Controller (BMC). The communication to the BMC
is available either through an on-board System Management Bus
(SMBus) port or through the DMTF defined NC-SI. The controller
provides filtering capabilities to determine which traffic is forwarded
to the host. For low-cost implementation, the internal controller
supports ASF 2.0.
PCI Express* Features
PCI Express* 2.0 (2.5 Gbps)
• Compatible extensions to PCI power management and ACPI
• Wake on LAN feature supported
Gigabit MAC/PHY Advanced Features
Intel® I/O Acceleration Technology (Intel® I/OAT)
Wide, pipelined internal data path architecture
MSI-X support
Mechanism available for reducing interrupts generated from
Tx/Rx operations
Low-latency interrupts
Four optimized Transmit (Tx) and Receive (Rx) queues per port
Caches up to 64 packet descriptors per queue
Dual 48 KB configurable Rx and Tx first-in/first-out
(FIFO) buffers
Support for transmission and reception of packets up to
9.5 KBytes (Jumbo Frames)
Programmable host memory receive buffers size per queue
(1 KByte to 127 KBytes) and cache line size (64 Bytes or 128 Bytes)
Descriptor ring management hardware for Tx/Rx optimized descriptor
fetching and write-back mechanisms
IEEE 802.3* auto-negotiation
IEEE 802.3* compliant flow-control support with
software-controllable pause times and threshold values
Supported cable length is more than 100 meters
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3 PHY compliance and compatibility
Built-in cable diagnostics and adjustments for cable faults
Host Offloading Features
VMDq
Direct Cache Access (DCA)
Header split and replication in receive
Features
Benefits
• Supports x4/x2 lanes
• Supports configurable completion timeout
• Efficient power management
• Accelerated TCP I/O for improved CPU utilization
• Low-latency data handling
• Superior direct memory access (DMA) transfer-rate performance
• Minimizes the overhead of interrupts
• Allows load balancing of interrupt handling between different cores/CPUs
• Maximizes system performance and throughput
• Provides the ability to toggle between interrupt aggregation and non-aggregation mode based
• Network packet handling without waiting or buffer overflow
• Efficient packet prioritization
• Efficient use of PCI Express bandwidth
• No external FIFO memory requirements
• FIFO size adjustable to application
• Error detection and correction for FIFO data
• Enables higher and better throughput of data
• Efficient use of PCI Express bandwidth and memory resources
• Simple software programming model
• Efficient use of system memory and PCI Express bandwidth
• Automatic link configuration for speed, duplex, and flow control
• Improves performance and reliability
• Frame loss from receive overruns reduced
• Control over the transmissions of pause frames through software or hardware triggering
• Reliable operation at greater distances
• Smaller footprint, lower power dissipation compared to multi-chip MAC and PHY solutions
• Robust operation over installed base of Category-5 twisted-pair cabling
• Improved end-user troubleshooting
• Tolerance of common wiring faults
• Allows the efficient routing of packets to the correct target machine in a virtualized
• Enables the I/O device to activate a pre-fetch engine in the CPU that loads the data into the
• Helps the driver to focus on the relevant part of the packet without the need to parse it
on the type of data being transferred
environment using multiple hardware queues
CPU cache ahead of time, before use, eliminating cache misses and reducing CPU load
Device Configuration
The Intel 82575EB Gigabit Ethernet Controller can be configured
using the EEPROM, but can also be used in an EEPROM-less config-
uration. The internal PHYs can be controlled using an internal IEEE
802.3 MDIO register set. External PHYs can be controlled using either
an IEEE 802.3 MDIO interface or using a 2-wire interface as defined
in the SFP module specification. Both of the ports support the Wake
on LAN feature.
The Intel 82575EB Gigabit Ethernet Controller package is a 25 mm
x 25 mm, 576-pin Flip-Chip Ball Grid Array (FC-BGA).