A3PN060-VQG100 Actel, A3PN060-VQG100 Datasheet - Page 51

• Manufacturer Part Number: A3PN060-VQG100
• Manufacturer: Actel

Figure 2-13 • Output Register Timing Diagram
Table 2-55 • Output Data Register Propagation Delays
Enable
CLK
Preset
Clear
DOUT
Data_out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Output Register
Timing Characteristics
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30
Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.22 0.25 0.30
Clock Minimum Pulse Width HIGH for the Output Data Register
Clock Minimum Pulse Width LOW for the Output Data Register
Commercial-Case Conditions: T
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
Description
50%
J
50%
= 70°C, Worst-Case V
50%
t
A dv a n c e v 0. 2
OWPRE
t
OPRE2Q
50%
50%
t
t
ORECPRE
50%
OCLR2Q
50%
t
OWCLR
50%
50%
CC
ProASIC3 nano DC and Switching Characteristics
50%
= 1.425 V
t
ORECCLR
Table 2-6 on page 2-5
50%
t
OCKMPWH
0.59 0.67 0.79
0.31 0.36 0.42
0.00 0.00 0.00
0.80 0.91 1.07
0.80 0.91 1.07
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.36 0.41 0.48
0.32 0.37 0.43
–2
t
50%
OREMPRE
t
50%
OCKMPWL
–1
for derating
Std. Units
t
OREMCLR
50%
50%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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