XRP7714ILB-0X18-F Exar Corporation, XRP7714ILB-0X18-F Datasheet - Page 19

• Manufacturer Part Number: XRP7714ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7714ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 4.75 V ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1699

S
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250µs steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
P
The XRP7714 allows the user to set the upper and lower bound for a power good signal per
channel.
SET_PWRG_TARG_MIN_CHx register sets the lower bound. Each register has a 20mV LSB
resolution. When the output voltage is within bounds the power good signal is asserted high.
Typically the upper bound should be lower than the over-voltage threshold. In addition, the power
good signal can be delayed by a programmable amount set in the SET_PWRGD_DLY_CHx register.
The power good delay is only set after the soft-start period is finished. If the channel has a pre-
charged condition that falls into the power good region, a power good flag is not set until the soft-
start is finished.
PWM S
The PWM switching frequency is set by choosing the corresponding oscillator frequency and clock
divider ratio in the SET_SW_FREQUENCY register. Bits [6:4] set the oscillator frequency and bits
[2:0] set the clock divider. The tables below summarize the available Main Oscillator and PWM
switching frequency settings in the XRP7714.
© 2011 Exar Corporation
Main Oscillator Frequency
OFT
OWER
SET_SW_FREQUENCY[6:4]
-S
Main Oscillator Frequency
TOP
G
WITCHING
OOD
The
Ts
F
Enable
Signal
Vout
LAG
SET_PWRG_TARG_MAX_CHx
F
REQUENCY
48MHz
20.8ns
000
Q
Q
Fig. 25: Channel Soft-Stop Sequence
u
u
a
a
DELAY
Bit [10:15]
d
d
44.8MHz 41.6MHz 38.4MHz 35.2MHz
22.3ns
001
C
C
h
h
a
a
19/29
n
n
n
n
24ns
e
e
PD_DELAY_CHx
010
register
l
l
REGISTER
D
D
i
i
g
g
i
i
t
26ns
t
011
a
a
l
l
sets
Fall Time
P
P
W
W
Bit [0:9]
28.4ns
M
100
M
the
S
S
t
t
e
e
31.25ns
p
p
32MHz
101
upper
D
D
o
o
w
w
28.8Mhz
n
n
34.7ns
110
X
X
bound,
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.6
t
t
7
7
25.6MHz
r
r
39ns
o
o
111
7
7
l
l
1
1
l
l
the
e
e
4
4
r
r