XRP7714ILB-0X18-F Exar Corporation, XRP7714ILB-0X18-F Datasheet - Page 23

• Manufacturer Part Number: XRP7714ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7714ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 4.75 V ~ 25 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1699

P
Each switching channel is configured to run with a phase shift of 90 degrees.
GPIO P
The General Purpose Input Output (GPIO) Pins are the basic interface between the XRP7714 and
the system. Although all of the stored data within the IC can be read back using the I2C bus it is
sometimes convenient to have some of those internal register to be displayed and or controlled by
a single data pin. Besides simple input output functions the GPIO pins can be configured to serve
as external clock inputs. These pins can be programmed using OTP bits or can be programmed
using the I
functions that the GPIO can be programmed to do.
NOTE: the GPIO Pins (and all I/Os) should NOT be driven without a 10K resistor when VIN is not
being applied to the IC.
The polarity of the GPIO pin can be set by using the GPIO_ACT_POL register. This register allows
any GPIO pin whether configured as an input or output to change polarity. Bits [5:0] are used to
set the polarity of GPIO 0 though 5. If the IC operates in I
[5:4] are ignored.
Each GPIO can be configured to enable a specific power rail for the system.
register allows a GPIO to enable/disable any of the following rails controlled by the chip:
When the configured GPIO is asserted externally, the corresponding rails will be enabled, and they
will be similarly disabled when the GPIO is de-asserted. This supply enabling/disabling can also be
controlled through the I
The GPIO pins can be configured as Power Good indicators for one or more rails. The GPIO pin is
asserted when all rails configured for this specific IO are within specified limits for regulation. This
information can also be found in the READ_PWRGD_SS_FLAG status register.
© 2011 Exar Corporation
GPIO Pins Polarity
Supply Rail Enable
Power Good Indicator
HASE
•
•
•
A single buck power controller
The Standby LDO
Any mix of the Standby LDO and power controller(s)
S
INS
HIFT
2
C bus. This GPIO_CONFIG register allows the user close to 100 different configuration
CLK_IN
Fig. 30:Alternative External clock synchronization Master Slave combination
2
C interface.
external clock sync
GPIO3
Configured as a
master with
Q
Q
XRP7714
u
u
a
a
GPIO1
d
d
GPIO2
C
C
h
h
CLK_OUT
a
SYNC_OUT
a
23/29
n
n
n
n
e
e
l
l
D
D
i
i
g
g
i
i
SYNC_IN
t
t
CLK_IN
a
a
2
C mode, then the commands for Bits
l
l
P
P
W
W
GPIO2
GPIO1
M
M
configured
XRP7714
as slave
S
S
t
t
e
e
p
p
D
D
o
o
w
w
The GPIOx_CFG
n
n
X
X
C
C
R
R
o
o
n
P
n
P
Rev. 1.1.6
t
t
7
7
r
r
o
o
7
7
l
l
1
1
l
l
e
e
4
4
r
r