XRP7740ILB-0X18-F Exar Corporation, XRP7740ILB-0X18-F Datasheet - Page 18

• Manufacturer Part Number: XRP7740ILB-0X18-F
• Description: IC CTRLR PWM/LDO STP-DWN 40TQFN
• Manufacturer: Exar Corporation
• Series: -r

Specifications of XRP7740ILB-0X18-F

• Topology: Step-Down (Buck) Synchronous (4), Linear (LDO) (1)
• Function: Any Function
• Number Of Outputs: 5
• Frequency - Switching: 1.5MHz
• Voltage/current - Output 1: Controller
• Voltage/current - Output 2: Controller
• Voltage/current - Output 3: Controller
• W/led Driver: No
• W/supervisor: No
• W/sequencer: Yes
• Voltage - Supply: 6.5 V ~ 20 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1697

CHIP OPERATION AND CONFIGURATION
S
The SET_SS_RISE_CHx register is a 16 bit register which specifies the soft-start delay and the
ramp characteristics for a specific channel. This register allows the customer to program the
channel with a 250us step resolution and up to a maximum 16ms delay.
Bits [15:10] specify the delay after enabling a channel but before outputting pulses; where each bit
represents 250us steps. Bits [9:0] specify the rise time of the channel; these 10 bits define the
number of microseconds for each 50mV increment to reach the target voltage.
S
The SET_PD_FALL_CHx register is a 16 bit register. This register specifies the soft-stop delay and
ramp (fall-time) characteristics for when the chip receives a channel disable indication from the
Host to shutdown the channel.
Bits [15:10] specify the delay after disabling a channel but before starting the shutdown of the
channel; where each bit represents 250us steps. Bits [9:0] specify the fall time of the channel;
these 10 bits define the number of microseconds for each 50mV increment to reach the discharge
threshold.
© 2011 Exar Corporation
OFT
OFT
-S
-S
TART
TOP
Enable
Signal
Vout
Enable
Signal
Vout
Q
Q
Fig. 20: Channel Power Up Sequence
Fig. 23: Channel Soft-Stop Sequence
u
u
a
a
d
d
DELAY
Bit [10:15]
Bit [10:15]
C
C
DELAY
h
h
a
a
n
n
18/28
n
n
e
e
SS_RISE_CHx
REGISTER
PD_DELAY_CHx
l
l
REGISTER
D
D
i
i
g
g
i
i
t
t
a
a
l
l
Fall Time
P
P
X
Bit [0:9]
X
W
W
RISE TIME
Bit [0:9]
R
R
M
M
P
P
S
S
7
7
t
t
7
7
e
e
0
0
p
p
8
8
D
D
o
o
a
a
w
w
n
n
n
d
n
d
C
C
X
X
o
o
R
R
n
n
P
P
t
t
Rev. 1.2.0
r
r
7
7
o
o
7
7
l
l
l
l
e
e
4
4
r
r
0
0
s
s