CY7C4801-25AC Cypress Semiconductor Corp, CY7C4801-25AC Datasheet
CY7C4801-25AC
Specifications of CY7C4801-25AC
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CY7C4801-25AC Summary of contents
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... Features • Double high speed, low power, first-in first-out (FIFO) memories • Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double (CY7C4821) • Double (CY7C4831) • Double (CY7C4841) • Double (CY7C4851) • Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package • ...
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... CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 10 CY7C4851 WCLKA 11 WENA1 12 RSA CY7C4801/4811/4821 CY7C4831/4841/4851 LDA LDB EFA PAEA PAFA FFA EFB PAEB PAFB FFB READ POINTER B READ CONTROL B RCLKB RENB1 48X1–1 RENB2 FFB EFB 46 45 OEB 44 RENB2 43 RCLKB 42 RENB1 GND PAEB 38 PAFB 37 DB ...
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... TQFP 64-pin TQFP Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 +150 C Operating Range +125 C Range 0.5V to +7.0V Commercial [1] Industrial 0.5V to +7.0V Notes: 0.5V to +7. the “instant on” case temperature CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1- CY7C4841 CY7C4851 ...
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... FIFO. PAF is synchronized to WCLK. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When (OEA,OEB) is LOW, the FIFO’s data outputs drive the bus to which they are connected. If (OEA,OEB) is HIGH, the FIFO’s outputs are in High Z (high-impedance) state. 4 CY7C4801/4811/4821 CY7C4831/4841/4851 ...
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... IH < V < Com’l 60 Ind 70 Test Conditions MHz 5.0V CC [6, 7] 3.0V R2 GND 680 3 ns 48X1–4 1.91V . 5 CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-15 7C48X1-25 7C48X1-35 Min. Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 0.4 2.0 V 2 0.5 0.8 0.5 ...
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... Flag Notes: 8. Pulse widths less than minimum values are not allowed. 9. Values guaranteed by design, not currently tested. 7C48X1-10 7C48X1-15 Min. Max. Min. Max. 100 66 4.5 6 4.5 6 3.5 4 0.5 1 3 CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1-35 Min. Max. Min. Max. Unit 40 28.6 MHz ...
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... CLK t t CLKH CLKL t ENH NO OPERATION t REF [11] t SKEW1 7 CY7C4801/4811/4821 CY7C4831/4841/4851 ENH NO OPERATION NO OPERATION t WFF t REF VALID DATA t OHZ , then (FFA,FFB) may not change state until the SKEW1 , then (EFA,EFB) may not change state until the next SKEW1 48X1–6 ...
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... Holding (WENA2/LDA,WENB2/LDB) HIGH during reset will make the pin act as a second enable pin. Holding(WENA2/LDA,WENB2/LDB) LOW during reset will make the pin act as a load enable for the programmable flag offset registers RSR RSS t t RSR RSS t t RSS RSR t RSF t RSF t RSF 8 CY7C4801/4811/4821 CY7C4831/4841/4851 [13] OEA(OEB)=1 48X1–8 OEA(OEB)=0 ...
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... The Latency Timing applies only at the Empty Boundary (EFA, EFB= LOW). 16. The first word is available the cycle after (EFA, EFB) goes HIGH, always FRL t REF OLZ When t < minimum specification, t CLK SKEW1 SKEW1 9 CY7C4801/4811/4821 CY7C4831/4841/4851 48X1–9 (maximum) = either 2 FRL CLK SKEW1 CLK SKEW1 . ...
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... DATA WRITE1 ( ENH ENS WENA1(WENB1 ENS ENH WENA2(WENB2) (if applicable) t FRL RCLKA(RCLKB) t SKEW1 EFA(EFB) RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB) DATA IN OUTPUT REGISTER ( [15 REF REF CY7C4801/4811/4821 CY7C4831/4841/4851 DATA WRITE2 t ENH t ENS t t ENH ENS [15] t FRL t t REF SKEW1 DATA READ 48X1–10 ...
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... FFA(FFB) WENA1(WENB1) WENA2(WENB2) (if applicable) RCLKA(RCLKB) t ENS RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB DATA IN OUTPUT REGISTER WRITE t DS DATA WRITE t WFF t ENH t A DATA READ 11 CY7C4801/4811/4821 CY7C4831/4841/4851 NO WRITE [10] DATA WRITE t SKEW1 t t WFF WFF t ENH t ENS t A NEXT DATA READ 48X1–11 ...
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... If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW. 21. (PAFA,PAFB) offset = m. 22. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841, 8192-m words for CY7C4851. ...
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... WENA2/LDA (WENB2/LDB) t ENS RENA1, RENA2 (RENB1,RENB2 ( CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB t CLKL t ENH t A UNKNOWN PAE OFFSET LSB 13 CY7C4801/4811/4821 CY7C4831/4841/4851 PAF OFFSET LSB MSB 48X1–14 PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB 48X1–15 ...
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... The contents of the offset registers can be read to the data outputs when (WENA2/LDA, WENB2/LDB) is LOW and both (RENA1,RENB1) and (RENA2,RENB2) are LOW. LOW-to-HIGH transitions of (RCLKA,RCLKB) read register contents to the data out- puts. Writes and reads should not be preformed simultaneously on the offset registers. 14 CY7C4801/4811/4821 CY7C4831/4841/4851 (WENA2/LDA, WENB2/LDB) and (WENA2/LDA, WENB2/LDB) and ...
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... LOW-to-HIGH transition of (WCLKA,WCLKB) by one flip-flop and is set LOW when the number of unread words in the FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811 (512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841 (4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of available memory locations is greater than m ...
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... Read operations are inhibited whenever (EFA,EFB) is LOW, regard- less of the state of (RENA1,RENB1) and (RENA2,RENB2. (EFA,EFB) is synchronized to (RCLKA,RCLKB), i.e exclusively Full Flag CY7C4811 CY7C4821 0 [25] [25 (n+1) to (1024 (m+1)) [26] [26] to 511 (1024 m) 1024 CY7C4851 0 [25 [26] to 4095 (8192 m) to 8191 8192 16 CY7C4801/4811/4821 CY7C4831/4841/4851 FF PAF PAE 1023 PAF PAE ...
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... RESET (RSA,RSB) ( DATA OUT READ CLOCK (RCLKA,RCLKB) CY7C4801 READ ENABLE 1 (RENA1,RENB1) CY7C4811 CY7C4821 CY7C4831 OUTPUT ENABLE (OEA,OEB) CY7C4841 CY7C4851 PROGRAMMABLE(PAEA,PAEA) EMPTY FLAG (EFA,EFB) Read Enable 2 (RENA2,RENB2) Used in a Single Device Configuration. 17 CY7C4801/4811/4821 CY7C4831/4841/4851 QA ( 48X1–16 ...
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... WRITE ENABLE 2/LOAD WEN2/LD FFA FULL FLAG FFB Read Enable 2 Figure 3. Block Diagram of two FIFOs contained in one CY7C4801/4811/4821/4831/4841/4851 configured for an 18-bit When the CY7C4801/4811/4821/4831/4841/4851 Width Expansion Configuration, the Read Enable 2 (RENA2 and RENB2) control unputs can be grounded (see Figure this configuration, ...
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... Bidirectional Configuration The two FIFOs of the CY7C4801/4811/4821/4831/4841/4851 can be used to buffer data flow in two directions. In the exam- ple that follows, processor A can write data to processor B via PROCESSOR A CLOCK ADDRESS CONTROL DATA 9 RAM 9 Figure 4. Block Diagram of Bidirectional Configuration. Depth Expansion CY7C4801/4811/4821/4831/4841/4851can be adapted to ap- pliations that require greater than 256/512/1024/2048/4096/ 8192 words ...
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... Ordering Information Double 256x9 FIFO Speed Package (ns) Ordering Code 10 CY7C4801-10AC CY7C4801-10AI 15 CY7C4801-15AC CY7C4801-15AI 25 CY7C4801-25AC CY7C4801-25AI 35 CY7C4801-35AC CY7C4801-35AI Double 512x9 FIFO Speed Package (ns) Ordering Code 10 CY7C4811-10AC CY7C4811-10AI 15 CY7C4811-15AC CY7C4811-15AI 25 CY7C4811-25AC CY7C4811-25AI 35 CY7C4811-35AC CY7C4811-35AI Double 1Kx9 FIFO Speed Package (ns) Ordering Code 10 CY7C4821-10AC CY7C4821-10AI ...
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... Thin Quad Flatpack A65 64-Lead Thin Quad Flatpack A65 64-Lead Thin Quad Flatpack A65 64-Lead Thin Quad Flatpack A65 64-Lead Thin Quad Flatpack A65 64-Lead Thin Quad Flatpack 21 CY7C4801/4811/4821 CY7C4831/4841/4851 Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 64-Lead Thin Plastic Quad Flat Pack A65 CY7C4801/4811/4821 CY7C4831/4841/4851 ...