CY7C150-15PC Cypress Semiconductor Corp, CY7C150-15PC Datasheet - Page 3

• Manufacturer Part Number: CY7C150-15PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C150-15PC

• Density: 4Kb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 10b
• Package Type: PDIP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 90mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Word Size: 4b
• Number Of Words: 1K
• Lead Free Status / Rohs Status: Not Compliant

Switching Characteristics
Document #: 38-05024 Rev. *A
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
RC
AA
OHA
ACS
LZCS
HZCS
DOE
LZOE
HZOE
WC
SCS
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
RRC
SAR
SWER
SCSR
PRS
HCSR
HWER
HAR
LZRS
HZRS
5.
6.
7.
8.
READ CYCLE
WRITE CYCLE
RESET CYCLE
Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
At any given temperature and voltage condition, t
t
The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
OL
HZCS
/I
OH
, t
HZOE
and 30-pF load capacitance.
, t
Read Cycle Time
Address to Data Valid
Output Hold from Address
Change
CS LOW to Data Valid
CS LOW to Low Z
CS HIGH to High Z
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Reset Cycle Time
Address Valid to Beginning of
Reset
Write Enable HIGH to Beginning
of Reset
Chip Select LOW to Beginning of
Reset
Reset Pulse Width
Chip Select Hold After End of
Reset
Write Enable Hold After End of
Reset
Address Hold After End of Reset
Reset HIGH to Output in Low Z
Reset LOW to Output in
High Z
HZR
[8]
, and t
[6,7]
HZWE
Description
are tested with C
[6]
[6]
[6,7]
[6]
[6,7]
[6,7]
Over the Operating Range
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
HZ
[6]
is less than t
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
7C150 10
10
10
20
10
10
2
0
0
6
8
2
2
6
6
2
0
0
0
0
0
8
0
LZ
for any given device.
10
8
6
6
6
6
6
[2,5]
7C150 12
12
12
10
24
12
12
12
2
0
0
8
2
2
8
8
2
0
0
0
0
0
0
12
10
8
8
8
8
8
7C150 15
15
15
13
30
15
15
15
11
11
11
2
0
0
2
2
2
0
0
0
0
0
0
15
12
10
12
12
11
9
7C150 25
25
25
15
20
15
15
50
20
30
30
2
0
0
5
5
5
0
0
0
0
0
0
25
15
20
15
20
20
20
7C150 35
35
35
20
30
20
20
70
30
40
40
2
0
0
5
5
5
0
0
0
0
0
0
CY7C150
Page 3 of 11
35
20
25
20
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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