TE28F800B3BA90 Intel, TE28F800B3BA90 Datasheet
TE28F800B3BA90
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TE28F800B3BA90 Summary of contents
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... TSOP and 48-ball µBGA* packages. Additional information about this product family can be obtained by accessing Intel’s website at: http:// www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Datasheet ® ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800 548-4725 or by visiting Intel's website at http://www.intel.com. ...
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Contents 1.0 Introduction ..................................................................................................................7 1.1 Nomenclature ........................................................................................................7 1.2 Conventions ..........................................................................................................7 2.0 Functional Overview 3.0 Functional Overview 3.1 Architecture Diagram...........................................................................................10 3.2 Memory Maps and Block Organization ...............................................................10 3.2.1 Parameter Blocks ...................................................................................10 3.2.2 Main Blocks ............................................................................................11 3.2.3 4-, 8-, 16-, 32-, and ...
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Standby Power ....................................................................................... 51 9.4.4 Deep Power-Down Mode ....................................................................... 51 10.0 Operations Overview 10.1 Bus Operations ................................................................................................... 52 10.1.1 Read....................................................................................................... 52 10.1.2 Output Disable ....................................................................................... 53 10.1.3 Standby .................................................................................................. 53 10.1.4 Deep Power-Down / Reset..................................................................... ...
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... BGA package top side mark information added (Section CCS Added Command Sequence Error Note (Table 7) Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash -006 Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes ...
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Number -008 4-Mbit packaging and addressing information corrected throughout document -009 Corrected 4-Mbit memory addressing tables in Appendices D and E Max I -010 V CC Added 64-Mbit density and faster speed offerings -011 Removed access ...
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... Introduction This datasheet describes the specifications for the Intel device (hereafter referred to as the B3 flash memory device optimized for portable, low- power, systems. This family of products features 3.6 V I/Os, and a low V /V operating range of 2 3.6 V for Read, Program, and Erase operations. In addition, it ...
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... Max is 3 0.25 m 32-Mbit devices. CC 3.0 Functional Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: V Erase operation. All B3 flash memory devices provide program/erase capability at 2 (for fast production programming), and read with V flash memory a large percentage of the time, 2 ...
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... The B3 flash memory device family is available in either x8 or x16 packages in the following densities (see Appendix C, “Ordering Information,” • 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes of 8-bits each • 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or 2048 Kbytes of 8-bits each • ...
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... Memory Maps and Block Organization The B3 flash memory device is an asymmetrically blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up to 100,000 times. For the address locations of each block, see the following memory maps: • ...
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... After the parameter blocks, the remainder of the array is divided into equal-size main blocks (65,536 bytes/32,768 words) for data or code storage. The 8-Mbit device contains 15 main blocks; 16-Mbit flash has 31 main blocks; 32-Mbit has 63 main blocks; 64-Mbit has 127 main blocks. 3.2.3 4-, 8-, 16-, 32-, and 64-Mbit Word-Wide Memory Maps Table 2 ...
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Table 2. 16- and 32-Mbit Word-Wide Memory Addressing Map (Sheet 40000-47FFF 32 38000-3FFFF 32 30000-37FFF 32 28000-2FFFF 32 20000-27FFF 32 18000-1FFFF 32 10000-17FFF 32 08000-0FFFF 32 00000-07FFF This column continues on next ...
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Table 2. 16- and 32-Mbit Word-Wide Memory Addressing Map (Sheet 16-Mbit and 32-Mbit Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit (KW ...
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Table 3. 4- and 8-Mbit Word-Wide Memory Addressing Map 4-Mbit and 8-Mbit Word-Wide Memory Addressing Top Boot Size 4 Mbit (KW) 3F000-3FFFF 7F000-7FFFF 3E000-3EFFF 7E000-7EFFF 3D000-3DFFF 7D000-7DFFF 3C000-3CFFF 7C000-7CFFF 3B000-3BFFF 7B000-7BFFF 3A000-3AFFF 7A000-7AFFF 39000-39FFF 79000-79FFF 38000-38FFF ...
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Table 4. 16-, 32-, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Size 16 Mbit 32 Mbit (KW) 4 FF000-FFFFF 1FF000-1FFFFF 4 FE000-FEFFF 1FE000-1FEFFF 4 FD000-FDFFF 1FD000-1FDFFF 4 FC000-FCFFF ...
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Table 4. 16-, 32-, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 08000-0FFFF 108000-10FFFF 32 00000-07FFF 100000-107FFF 32 0F8000-0FFFFF 32 0F0000-0F7FFF 32 0E8000-0EFFFF 32 0E0000-0E7FFF 32 0D8000-0DFFFF 32 0D0000-0D7FFF 32 0C8000-0CFFFF 32 0C0000-0C7FFF ...
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Table 4. 16-, 32-, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit 32 Mbit (KW) 32 0A8000-0AFFFF 32 0A0000-0A7FFF 32 098000-09FFFF 32 090000-097FFF 32 088000-08FFFF ...
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Table 4. 16-, 32-, and 64-Mbit Word-Wide Memory Addressing Map (Sheet This column continues on next ...
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Table 4. 16-, 32-, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing (Continued) Top Boot Size 16 Mbit 32 Mbit (KW ...
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Byte-Wide Memory Maps Table 5. 8- and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Size (KB) 8 Mbit 8 FE000-FFFFF ...
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Table 5. 8- and 16-Mbit Byte-Wide Memory Addressing Map (Sheet This column continues on next page Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 050000-05FFFF 64 040000-04FFFF 64 030000-03FFFF 64 020000-02FFFF 64 010000-01FFFF 64 ...
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Table 5. 8- and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 8-Mbit and 16-Mbit Byte-Wide Memory Addressing (Continued) Top Boot Size (KB) 8 Mbit ...
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Table 6. 4-Mbit Byte Wide Memory Addressing Map Top Boot Size 4 Mbit (KB) 8 7E000-7FFFF 8 7C000-7DFFF 8 7A000-7BFFF 8 78000-79FFF 8 76000-77FFF 8 74000-75FFF 8 72000-73FFF 8 70000-71FFF 64 60000-6FFFF 64 50000-5FFFF 64 40000-4FFFF 64 30000-3FFFF 64 20000-2FFFF ...
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Package Information 4.1 BGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package Figure 2. BGA* and VF BGA Package Drawing Ball A1 D Corner ...
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TSOP Package Figure 3. TSOP Package Drawing Z Pin 1 Detail B b Dimensions Package Height Standoff Package Body Thickness Lead Width Lead Thickness Plastic Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count ...
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Easy BGA Package Figure 4. Easy BGA Package Drawing Ball A1 Corner Top View - Ball side down A1 A2 Dimensions Table Package ...
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... Pinout and Signal Descriptions This section explains the package pinout and signal descriptions. 5.1 Signal Pinouts The B3 flash memory device is available in 40-lead TSOP (x8, Figure 6), 48-ball BGA(x8 and x16, (x16, Figure 9) packages. 5.1.1 40-Lead and 48-Lead TSOP Packages Figure 5. 40-Lead TSOP Package for x8 Configurations ...
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... Current Mark: New Mark: Note: The topside marking on 8-Mb, 16-Mb, and 32-Mb Intel TSOP products will convert to a white ink triangle as a Pin-1 indicator. Products without the white triangle will continue to use a dimple as a Pin-1 indicator. There are no other changes in package size, materials, functionality, customer handling, or manufacturability ...
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... TE28F160B3TC80 TE28F016B3BA90 TE28F160B3TA90 TE28F016B3BA110 TE28F160B3TA110 TE28F008B3BA90 TE28F800B3TA90 TE28F008B3BA110 TE28F800B3TA110 16M A12 A10 W E# RP# A19 A13 A11 69. 48-Lead TSOP TE28F640B3BC70 TE28F320B3BD70 TE28F320B3BC70 TE28F320B3BC90 TE28F320B3BA100 TE28F320B3BA110 TE28F160B3BC70 TE28F160B3BC80 TE28F160B3BA90 TE28F160B3BA110 TE28F800B3BA90 TE28F800B3BA110 A20 A7 A4 A18 CE GND NC D1 OE# 0580_04 is the upgrade address for 20 29 ...
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... NOTES: 1. A19, A20, and A21 indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Intel recommends that routing is not done in this area. A the 16-Mbit device device. 2. Table 8, “B3 Flash memory Device Signal Descriptions” on page 31 ...
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... Signal Descriptions Table 8, “B3 Flash memory Device Signal Descriptions” on page Table 8. B3 Flash memory Device Signal Descriptions (Sheet Symbol Type ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. A –A Input 28F008B3: A[0-19], 28F016B3: A[0-20], ...
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... Table 8. B3 Flash memory Device Signal Descriptions (Sheet Symbol Type PROGRAM/ERASE Power Supply: Supplies power for Program and Erase operations the same as V manufacturing, 11 12.6 V can be supplied Power 2500 cycles on the parameter blocks maximum (see V < ...
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... Conditions” as extended exposure beyond the “Operating Conditions” can affect device reliability. NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design Table 9. Absolute Maximum Ratings ...
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Operating Conditions Table 10. Temperature and Voltage Operating Conditions Symbol T Operating Temperature Supply Voltage CC1 CC V CC2 V CCQ1 V I/O Supply Voltage CCQ2 V CCQ3 V Supply Voltage PP1 ...
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Electrical Specifications 7.1 DC Current Characteristics Table 11. DC Current Characteristics (Sheet Sym Parameter V Note I Input Load Current LI I Output Leakage Current LO V Standby Current for CC 0.13 and 0.18 Micron ...
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Table 11. DC Current Characteristics (Sheet Sym Parameter V Note I V Program Current PPW Erase Current PPE Erase Suspend PPES CC I Current PPWS NOTES: ...
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DC Voltage Characteristics Table 12. DC Voltage Characteristics V 2.7 V–3 Symbol Parameter V 2.7 V–3.6 V CCQ Note Min Input Low V –0.4 IL Voltage Input High V 2.0 IH Voltage Output Low V –0.1 OL ...
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AC Characteristics 8.1 AC Read Characteristics Table 13. Read Operations—8-Mbit Density # Sym Parameter R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 ...
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Table 14. Read Operations—16-Mbit Density Density 70 ns Product Para- # Sym mete r 2.7 V–3 Min Read Cycle Time AVAV t Address to AVQ R2 Output Delay V t CE# to Output ELQ ...
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Table 15. Read Operations—32-Mbit Density Density 70 ns Product Para- # Sym meter 2.7 V–3 Min Max Read Cycle Time AVAV t Address to Output AVQ R2 Delay V t ...
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Table 16. Read Operations — 64-Mbit Density # Sym R1 t Read Cycle Time AVAV R2 t Address to Output Delay AVQV R3 t CE# to Output Delay ELQV R4 t OE# to Output Delay GLQV R5 t RP# to ...
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AC Write Characteristics Table 17. Write Operations—8-Mbit Density # Sym Parameter t / PHWL W1 RP# High Recovery to WE# (CE#) Going Low t PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) ...
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Table 18. Write Operations—16-Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) Going PHWL W1 t Low PHEL t / ELWL W2 CE# (WE#) Setup to WE# (CE#) Going Low t WLEL t / WLWH W3 ...
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Table 19. Write Operations—32-Mbit Density # Sym Parameter t / RP# High Recovery to WE# (CE#) PHWL W1 t Going Low PHEL t / CE# (WE#) Setup to WE# (CE#) ELWL W2 t Going Low WLEL ...
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Table 20. Write Operations—64-Mbit Density # Symbol RP# High Recovery to WE# (CE#) Going Low PHWL PHEL CE# (WE#) Setup to WE# (CE#) Going Low ELWL WLEL WE# ...
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Figure 11. Write Operations Waveform Address [A] CE# [E] WE# [W] OE# [G] Data [D/Q] W1 RP# [P] Vpp [ W10 Datasheet ...
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Erase and Program Timing Table 21. Erase and Program Timing Symbol 4-KW Parameter Block t BWPB Word Program Time 32-KW Main Block t BWMB Word Program Time Word Program Time for 0.13 and 0.18 Micron Product ...
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Figure 13. Transient Equivalent Testing Load Circuit NOTE: See Table 22 Table 22. Test Configuration Component Values for Worst Case Speed Conditions Test Configuration V Min Standard Test CCQ NOTE: C includes jig capacitance. L 8.5 ...
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... Power and Reset Specifications 9.1 Power-Up/Down Characteristics To prevent any condition that may result in a spurious write or erase operation, Intel recommends that you power-up V together. Intel also recommends power-up V powerdown with or slightly before and/or VPP are not connected to the V CCQ applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin. ...
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... Sampled, but not 100% tested. Figure 14. Deep Power-Down/Reset Operations Waveforms 9.3 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers must consider the following three supply current issues: 1. Standby current levels (I 2. Read current levels (I 3. Transient peaks produced by falling and rising edges of CE#. ...
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... Power Consumption Intel flash devices have a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower ...
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... The B3 flash memory device performs read, program, and erase in-system through the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE#, and RP#. ...
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... Block-Erase operations CPU reset occurs with no flash memory reset, proper CPU initialization can not occur because the flash memory may be providing status information instead of array data. Intel allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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WE# or CE# pulse, whichever occurs first. shows the available commands, and the different modes of operation using CUI commands. Two commands modify array data: Program (40H), ...
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... CUI before array reads can occur. Table 26. Command Codes and Descriptions (Sheet Code Device Mode 00, 01, Invalid/ Unassigned commands that must not be used. Intel reserves the right to redefine these codes 60, 2F, Reserved for future functions. C0 Read Array Places the device in read-array mode, such that array data will be output on the data pins ...
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... Status Register to “1,” but it cannot clear them to “0.” Issuing this Register command clears those bits to “0.” Puts the device into the intelligent-identifier-read mode, so that reading the device will output 90 Read Identifier the manufacturer and device codes (A address inputs must be 0) ...
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Read Status Register The device Status Register indicates when a Program or Erase operation is complete, and the success or failure of that operation. To read the Status Register, issue the Read Status Register (70H) command to the CUI. ...
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... After an Erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status- register reads advisable to place the flash in read-array mode after the erase is complete. 11.5.1 Suspending and Resuming Erase Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided to allow erase-sequence interruption in order to read data from— ...
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... Program/Erase Resume NOTES: PA: Program Address IA: Identifier Address 1. Bus operations are defined in 2. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes for manufacturer code Either 40H or 10H command is valid although the standard is 40H. 4. When writing commands to the device, the upper data bus [DQ minimize current draw ...
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... No operation to locked blocks SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTE: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set. 12.0 Block Locking The B3 flash memory device architecture features two hardware-lockable parameter blocks. 12.1 WP for Block Locking IL The lockable blocks are locked when WP block will result in an error, which will be reflected in the Status Register: • ...
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For the bottom configuration, the bottom two parameter blocks (blocks #0 and #1 for 4 /8 /16 / 32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless V is below V PP 12.2 WP# = ...
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... V Program and Erase Voltages PP TheB3 flash memory device products provide in-system programming and erase at 2.7 V. For customers requiring fast programming in their manufacturing environment, B3 flash memory device includes an additional low-cost 12-V programming feature. The 12-V V mode enhances programming performance during the short period of time typically PP found in manufacturing processes ...
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... IFDI Interactive: Play with Intel NOTES: 1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers must contact their local Intel or distribution sales office. 2. Visit the Intel home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. ...
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Appendix A Write State Machine Current/Next States Data Read Current State SR.7 When Array Read (FFH) Read Read Array “1” Array Array Read Read Status “1” Status Array Read Read “1” Identifier Identifier Array Prog. Setup ...
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Appendix B Program and Erase Flowcharts Figure 15. Program Flowchart Start Write 40H Program Address/Data Read Status Register SR Yes Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 ...
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Figure 16. Program Suspend/Resume Flowchart Start Write B0H Write 70H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Program Resumed 66 Operation Write Write Read ...
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Figure 17. Block Erase Flowchart Start Write 20H Write D0H and Block Address Read Status Register SR Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR ...
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Figure 18. Erase Suspend/Resume Flowchart Start Write B0H Write 70H Read Status Register SR SR Write FFH Read Array Data Done Reading Yes Write D0H Erase Resumed 68 Bus Operation Write Write ...
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... GT = 48- Ball µBGA * CSP BGA CSP RC = Easy BGA Free Easy BGA Free VFBGA Free TSOP Product line designator ® for all Intel Flash products Device Density 640 = x16 (64 Mbit ) 320 = x16 (32 Mbit ) 160 = x16 (16 Mbit ) 800 = x16 (8 Mbit ) Ordering Information: Valid Combinations Table 31 ...
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... TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 GT28F160B3TA90 TE28F160B3BC80 GT28F160B3BA90 TE28F160B3TC90 GT28F160B3TA110 TE28F160B3BC90 GT28F160B3BA110 TE28F160B3TA90 TE28F160B3BA90 TE28F160B3TA110 TE28F160B3BA110 JS28F160B3TA70 JS28F160B3BD70 TE28F800B3TA90 TE28F800B3BA90 TE28F800B3TA110 TE28F800B3BA110 Section 11.2, “Read Identifier” on page 56 Advanced Boot Block Products. (Sheet (1,2) 48-Ball VF BGA GE28F160B3TD70 GE28F160B3BD70 GE28F160B3TC70 (3) GE28F160B3BC70 (3) GE28F160B3TC80 (3) GE28F160B3BC80 ...