LH28F800SGHE-L10 Sharp Electronics, LH28F800SGHE-L10 Datasheet
LH28F800SGHE-L10
Specifications of LH28F800SGHE-L10
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LH28F800SGHE-L10 Summary of contents
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... SIMMs and memory cards. Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800SG-L/SGH-L offer three levels of protection : absolute protection with V ...
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COMPARISON TABLE VERSIONS OPERATING TEMPERATURE LH28F800SG +70˚C (FOR TSOP, CSP) LH28F800SGH-L – +85˚C (FOR TSOP, CSP) 1 LH28F800SG +70˚C (FOR SOP) 1 Refer to the datasheet of LH28F800SG-L (FOR SOP). PIN CONNECTIONS 48-PIN TSOP ...
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BLOCK DIAGRAM Y DECODER INPUT BUFFER ADDRESS LATCH X DECODER ADDRESS COUNTER LH28F800SG-L/SGH-L (FOR TSOP, CSP OUTPUT INPUT BUFFER BUFFER IDENTIFIER REGISTER STATUS REGISTER DATA COMPARATOR Y GATING 16 32 k-WORD BLOCKS ...
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... DEVICE POWER SUPPLY : Internal detection configured the device for 2 operation. To switch from one voltage to another, ramp V ramp V V SUPPLY CC attempts to the flash memory are inhibited. Device operations at invalid V (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GND SUPPLY GROUND : Do not float any ground pins. ...
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... Product Overview The LH28F800SG-L/SGH-L are high-performance 8 M-bit SmartVoltage flash memories organized as 512 k-word of 16 bits. The 512 k-word of data is arranged in sixteen 32 k-word blocks which are individually erasable, lockable, and unlockable in- system ...
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The selected block can be locked or unlocked individually by the combination of sixteen block lock bits and the RP# or WP#. Block erase or word write must not be carried out by setting block lock bits and setting WP# ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes, or status register independent of the V voltage ...
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... As with any automated device important to ), the device assert RP# during system reset. When the system IH -DQ are comes out of reset, it expects to read from the flash 0 15 memory. Automated flash memories provide status information when accessed during block erase, word write, or lock-bit configuration modes ...
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Read Identifier Codes The read identifier codes operation outputs the manufacture code, device code, block lock configuration codes for each block, and the permanent lock configuration code (see Fig. 2). Using the manufacture and device codes, the system CPU ...
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MODE NOTE Read Output Disable 3 Standby 3 Deep Power-Down 4 Read Identifier Codes 8 Write NOTES : 1. Refer to Section 6.2.3 "DC CHARACTERISTICS". ≤ V When V , ...
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BUS CYCLES COMMAND REQ Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume Set Block Lock-Bit Set Permanent Lock-Bit Clear Block Lock-Bits ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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Fig. 3). The CPU can detect block erase completion by analyzing the output data of the RY/BY# pin or status register bit SR.7. When the block erase is complete, status ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any ...
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If a clear block lock-bits operation is aborted due transition out of valid range or WP RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block ...
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WSMS ESS ECLBS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H, Address Write Word Data and Address Read Status Register Suspend Word No Write Loop 0 Yes Suspend SR.7 = Word Write 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Word Write or Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR Word Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write ...
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Start Write 60H, Block/Device Address Write 01H/F1H, Block/Device Address Read Status Register 0 SR Full Status Check if Desired Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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Start Write 60H Write D0H Read Status Register 0 SR Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above Range Error ...
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... GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V trace. The V pin supplies the memory cell current PP for word writing and block erasing ...
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... IL When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility or CE# PP increases usable battery life because data is retained when system power is removed. ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature • LH28F800SG-L During Read, Block Erase, Word Write, and Lock-Bit Configuration ........ 0 to +70°C Temperature under Bias ............ – +80°C • LH28F800SGH-L During Read, Block Erase, Word Write, ...
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CAPACITANCE SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a Logic ...
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V 1N914 DEVICE UNDER TEST Includes Jig L Capacitance Fig. 12 Transient Equivalent Testing Load Circuit LH28F800SG-L/SGH-L (FOR TSOP, CSP) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, ...
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DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power-Down CC I CCD Current I V Read Current CCR CC V Word Write ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL Output High Voltage V OH1 (TTL) Output High Voltage V OH2 (CMOS) V Lockout Voltage during PP V PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
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AC CHARACTERISTICS - READ ONLY OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) ( ...
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AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# ...
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AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to WE# t PHWL Going Low t CE# Setup to WE# ...
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V IH ADDRESSES ( AVAV V IH CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/Q) ...
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AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS • 2 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going ...
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AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to CE# t PHEL Going Low t WE# Setup to CE# ...
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V IH ADDRESSES ( AVAV V IH WE# ( WLEL V IH OE# ( CE# ( High Z DATA (D/Q) ...
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RESET OPERATIONS V OH RY/BY# ( RP# ( RY/BY# ( RP# ( 2.7 V/3.3 V RP# (P) V ...
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BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE • 2 +70˚C or – SYMBOL PARAMETER NOTE t WHQV1 Word Write Time t EHQV1 Block Write Time ...
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BLOCK ERASE, WORD WRITE AND LOCK-BIT CONFIGURATION PERFORMANCE (contd.) • 5.0±0.25 V, 5.0±0 SYMBOL PARAMETER t WHQV1 Word Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 t ...
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... ORDERING INFORMATION Product line designator for all SHARP Flash products ( Device Density 800 = 8 M-bit Architecture S = Symmetrical Block Power Supply Type G = SmartVoltage Technology Operating Temperature Blank = – + OPTION ORDER CODE 1.35 V I/O Levels 1 LH28F800SGXX-L70 2 LH28F800SGXX-L10 LH28F800SG-L/SGH-L (FOR TSOP, CSP) Access Speed (ns ...
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TSOP (TSOP048-P-1220 20.0 0.3 18.4 0.2 Package base plane 0.1 19.0 PACKAGING ...
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CSP (FBGA048-P-0808) 0.1 S 0.8 0 0.1 S TYP. 0 0.2 8 TYP. TYP 1.2 0.03 0. PACKAGING Land hole ...