LH28F800SGHE-L10 Sharp Electronics, LH28F800SGHE-L10 Datasheet - Page 8
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LH28F800SGHE-L10
Manufacturer Part Number
LH28F800SGHE-L10
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800SGHE-L10.pdf
(45 pages)
Specifications of LH28F800SGHE-L10
Cell Type
NOR
Density
8Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
19b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
TSOP-I
Program/erase Volt (typ)
2.7/3.3/5/12V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
16b
Number Of Words
512K
Supply Current
65mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH28F800SGHE-L10
Manufacturer:
SHARP
Quantity:
200
RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the
device selection control, and when active enables
the selected memory device. OE# is the data
output (DQ
the selected memory data onto the I/O bus. WE#
must be at V
Fig. 13 illustrates read cycle.
3.2 Output Disable
With OE# at a logic-high level (V
outputs are disabled. Output pins DQ
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device
power consumption. DQ
in a high-impedance state independent of OE#. If
deselected during block erase, word write, or lock-
bit configuration, the device continues functioning,
and consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low
for a minimum of 100 ns. Time t
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI is
reset to read array mode and status register is set
to 80H.
IL
0
initiates the deep power-down mode.
-DQ
IH
15
and RP# must be at V
) control and when active drives
0
-DQ
IH
) places the device in
15
outputs are placed
PHQV
IH
), the device
0
is required
IH
-DQ
or V
15
are
HH
.
- 8 -
During block erase, word write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be
partially erased or written. Time t
after RP# goes to logic-high (V
command can be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase,
word write, or lock-bit configuration modes. If a
CPU reset occurs with no flash memory reset,
proper CPU initialization may not occur because
the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In
this application, RP# is controlled by the same
RESET# signal that resets the system CPU.
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
IH
PHWL
) before another
is required