LH28F008BJT-TTLZ2 Sharp Electronics, LH28F008BJT-TTLZ2 Datasheet - Page 37
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LH28F008BJT-TTLZ2
Manufacturer Part Number
LH28F008BJT-TTLZ2
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F008BJT-TTLZ2.pdf
(44 pages)
Specifications of LH28F008BJT-TTLZ2
Cell Type
NOR
Density
8Mb
Access Time (max)
100ns
Interface Type
Parallel
Boot Type
Top
Address Bus
20b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
1M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
40
Lead Free Status / Rohs Status
Not Compliant
6.2.6 Alternative CE#-Controlled Writes
NOTES:
1. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid A
4. V
.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
PHEL
WLEL
ELEH
SHEH
VPEH
AVEH
DVEH
EHDX
EHAX
EHWH
EHEL
EHR0
EHGL
QVVL
QVSL
Sym.
WE# times should be measured relative to the CE# waveform.
success (SR.1/3/4/5=0).
CCW
should be held at V
Write Cycle Time
RP# High Recovery to CE# Going Low
WE# Setup to CE# Going Low
CE# Pulse Width
WP#V
V
Address Setup to CE# Going High
Data Setup to CE# Going High
Data Hold from CE# High
Address Hold from CE# High
WE# Hold from CE# High
CE# Pulse Width High
CE# High to SR.7 Going "0"
Write Recovery before Read
V
WP# V
CCW
CCW
IH
Hold from Valid SRD
Setup to CE# Going High
IH
Setup to CE# Going High
Hold from Valid SRD
CCWH1/2
IN
and D
Parameter
until determination of block erase, full chip erase, byte write or lock-bit configuration
IN
for block erase, full chip erase, byte write or lock-bit configuration.
V
CC
=2.7V-3.6V, T
(1)
A
=0°C to +70°C
Notes
2,4
2,4
2
2
2
3
3
Min.
100
100
100
50
50
50
20
1
0
0
0
0
0
0
0
Max.
100
Rev. 1.27
Unit
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns