LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet
LH28F008BVT-BTL10
Specifications of LH28F008BVT-BTL10
Available stocks
Related parts for LH28F008BVT-BTL10
LH28F008BVT-BTL10 Summary of contents
Page 1
... Flash Memory LH28F008BVT-BTL10 Date Dec. 11. 1998 ...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 2 PRINCIPLES OF OPERATION........................................ 6 2.1 Data Protection............................................................. 7 3 BUS OPERATION ............................................................ 7 3.1 Read.............................................................................. 7 3.2 Output Disable.............................................................. 7 3.3 Standby......................................................................... 7 3.4 Deep Power-Down ....................................................... 7 ...
Page 4
... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F008BVT-BTL10 offers two levels of protection: absolute protection with V at GND, selective hardware boot block locking ...
Page 5
... To take advantage of Smart3 technology, allow V and V connection to 2.7V-3.6V. PP 1.2 Product Overview The LH28F008BVT-BTL10 is a high-performance 8-Mbit Smart3 Flash memory organized as 1M-byte of 8 bits. The 1M-byte of data is arranged in two 8K-byte boot blocks, six 8K-byte parameter blocks and fifteen 64K-byte main blocks which are individually erasable in-system. ...
Page 6
Output Buffer Y Input Decoder Buffer X Address Latch Decoder Address Counter Figure 1. Block Diagram ...
Page 7
... DC Characteristics) produce spurious results and should not be attempted. PP DEVICE POWER SUPPLY: Do not float any power pins. With V V SUPPLY the flash memory are inhibited. Device operations at invalid V CC produce spurious results and should not be attempted. GND SUPPLY GROUND: Do not float any ground pins. ...
Page 8
... PRINCIPLES OF OPERATION The LH28F008BVT-BTL10 Smart3 Flash memory includes an on-chip WSM to manage block erase and byte write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure and byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode ...
Page 9
... Refer to Table 6 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes ...
Page 10
Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms ...
Page 11
Mode Notes Read 7 Output Disable Standby 8 Deep Power-Down 3,8 Read Identifier Codes 7 Write 5,6,7 NOTES: 1. Refer to DC Characteristics. When can for control pins and addresses, and V IL ...
Page 12
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 13
... SR.7 will return to "0". However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block or RP#= erase process ...
Page 14
... V The V PP complete write protection of all blocks in the flash device. 4.10.2 WP#=V The lockable blocks are locked when WP#=V program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable ...
Page 15
WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS ...
Page 16
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
Page 17
Start Write 40H or 10H, Address Write Byte Data and Address Read Status Register No 0 Suspend SR.7= Byte Write Yes 1 Full Status Check if Desired Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
Page 18
Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Read Byte Write Byte Write? Read Array Data Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block Erase ...
Page 19
Start Write B0H Read Status Register 0 SR.7= 1 Byte Write 0 SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Byte Write Read Array Data Resumed Figure 8. Byte Write Suspend/Resume Flowchart ...
Page 20
... PC board trace inductance. 5.3 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V Power supply trace. The V PP supplies the memory cell current for byte writing and block erasing ...
Page 21
... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle ) powers-up first. time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely is active ...
Page 22
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase and Byte Write...........................................0°C to +70°C Temperature under Bias ...................... -10°C to +80°C Storage Temperature ................................ -65°C to +125°C Voltage On Any Pin (except ...
Page 23
AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
Page 24
DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down Current CCD Read Current CCR Byte Write Current CCW ...
Page 25
Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during Normal PPLK PP Operations V V ...
Page 26
AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# ...
Page 27
Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
Page 28
AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP#V Setup to WE# ...
Page 29
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ WP#( RP#( ...
Page 30
ALTERNATIVE CE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP#V Setup to CE# Going High ...
Page 31
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ WP#( RP#( ...
Page 32
RESET OPERATIONS Device Device State Busy V IH RP#( 2. RP#( Sym. RP# Pulse Low Time t PLPH (If RP# is tied this specification is not ...
Page 33
BLOCK ERASE AND BYTE WRITE PERFORMANCE Sym. Parameter t Byte Write Time 64K byte Block WHQV1 t 8K byte Block EHQV1 Block Write Time 64K byte Block 8K byte Block t Block Erase Time 64K byte Block WHQV2 t ...
Page 34
... Such noises, when induced onto WE# signal or power supply, may be interpreted as false commands, causing undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) Protecting data in specific block By setting a WP# to low, only the boot block can be protected against overwriting ...
Page 35
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 36
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 37
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 38
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...