LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 9

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

2.1 Data Protection
Depending on the application, the system designer may
choose to make the V
(available only when memory block erases or byte writes
are required) or hardwired to V
accommodates either design practice and encourages
optimization of the processor-memory interface.
When V
The CUI, with two-step block erase or byte write
command sequences, provides protection from unwanted
operations even when high voltage is applied to V
write functions are disabled when V
lockout voltage V
boot blocks locking capability for WP# provides
additional protection from inadvertent code or data
alteration by block erase and byte write operations. Refer
to Table 6 for write protection alternatives.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the V
be at either V
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from deep power-down mode, the device
automatically resets to read array mode. Five control pins
dictate the data flow in and out of the component: CE#,
OE#, WE#, RP# and WP#. CE# and OE# must be driven
active to obtain data at the outputs. CE# is the device
selection control, and when active enables the selected
memory device. OE# is the data output (DQ
control and when active drives the selected memory data
onto the I/O bus. WE# must be at V
V
IH
or V
PP
HH
. Figure 11 illustrates read cycle.
V
IH
PPLK
or V
LKO
, memory contents cannot be altered.
HH
or when RP# is at V
.
PP
power supply switchable
IH
PPH1/2/3
CC
PP
and RP# must be at
is below the write
voltage. RP# can
IL
. The device
. The device’s
0
PP
-DQ
. All
7
)
3.2 Output Disable
With OE# at a logic-high level (V
are disabled. Output pins (DQ
impedance state.
3.3 Standby
CE# at a logic-high level (V
standby mode which substantially reduces device power
consumption. DQ
impedance state independent of OE#. If deselected during
block erase or byte write, the device continues
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time t
down until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase or byte write modes, RP#-low will
abort the operation. Memory contents being altered are no
longer valid; the data may be partially erased or written.
Time t
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase or byte write modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array data.
SHARP’s flash memories allow proper CPU initialization
following a system reset through the use of the RP# input.
In this application, RP# is controlled by the same RESET#
signal that resets the system CPU.
PHWL
IL
initiates the deep power-down mode.
is required after RP# goes to logic-high (V
PHQV
0
-DQ
is required after return from power-
7
outputs are placed in a high-
0
-DQ
IH
) places the device in
IH
7
) are placed in a high-
), the device outputs
Rev. 1.1
IH
)