LH28F320BFHE-PBTLF1 Sharp Electronics, LH28F320BFHE-PBTLF1 Datasheet - Page 13
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LH28F320BFHE-PBTLF1
Manufacturer Part Number
LH28F320BFHE-PBTLF1
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F320BFHE-PBTLF1.pdf
(47 pages)
Specifications of LH28F320BFHE-PBTLF1
Cell Type
NOR
Density
32Mb
Access Time (max)
80ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
21b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
2M
Supply Current
25mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Compliant
NOTES:
1. Bus operations are defined in Table 5.
2. All addresses which are written at the first bus cycle should be the same as the addresses which are written at the second
3. ID=Data read from identifier codes. (See Table 3 and Table 4).
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.
7. Following the third bus cycle, input the program sequential address and write data of "N" times. Finally, input the any
Read Array
Read Identifier Codes/OTP
Read Query
Read Status Register
Clear Status Register
Block Erase
Full Chip Erase
Program
Page Buffer Program
Block Erase and (Page Buffer)
Block Erase and (Page Buffer)
Set Block Lock Bit
Clear Block Lock Bit
Set Block Lock-down Bit
OTP Program
Set Partition Configuration Register
Program Suspend
Program Resume
bus cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See Table 3 and Table 4).
QA=Query codes address. Refer to Appendix of LH28F320BF series for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See Figure 3).
PCRC=Partition configuration register code presented on the address A
QD=Data read from query database. Refer to Appendix of LH28F320BF series for details.
SRD=Data read from status register. See Table 10 and Table 11 for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever
OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first)
N-1=N is the number of the words to be loaded into a page buffer.
configuration code, partition configuration register code and the data within OTP block (See Table 3 and Table 4).
The Read Query command is available for reading CFI (Common Flash Interface) information.
block can be erased or programmed when RST# is V
valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of
goes high first) during command write cycles.
during command write cycles.
Command
Cycles
Req’d
Bus
≥ 2
≥ 2
≥ 4
1
2
1
2
2
2
1
1
2
2
2
2
2
Table 6. Command Definitions
Notes
5,9
5,6
5,7
8,9
8,9
10
4
4
5
9
LHF32FF1
IH
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
.
(1)
First Bus Cycle
Addr
PCRC
WA
WA
BA
BA
BA
BA
OA
PA
PA
PA
PA
PA
PA
PA
X
(2)
0
-A
(11)
15
.
40H or
Data
B0H
D0H
C0H
FFH
E8H
90H
98H
70H
50H
20H
30H
10H
60H
60H
60H
60H
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Read
Read
Read
(1)
Second Bus Cycle
IA or OA
Addr
PCRC
WA
WA
OA
QA
BA
BA
BA
BA
PA
X
(2)
Rev. 2.44
ID or OD
Data
SRD
D0H
D0H
D0H
01H
2FH
04H
WD
N-1
QD
OD
10
(3)