LH28F320BFN-PTTLZJ Sharp Electronics, LH28F320BFN-PTTLZJ Datasheet - Page 14

• Manufacturer Part Number: LH28F320BFN-PTTLZJ
• Manufacturer: Sharp Electronics

Specifications of LH28F320BFN-PTTLZJ

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 2M
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

sharp
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
SR.15 - SR.8 = RESERVED FOR FUTURE
SR.6 = BLOCK ERASE SUSPEND STATUS (BESS)
SR.5 = BLOCK ERASE AND FULL CHIP ERASE
SR.4 = (PAGE BUFFER) PROGRAM AND
SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.2 = (PAGE BUFFER) PROGRAM SUSPEND
SR.1 = DEVICE PROTECT STATUS (DPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
ENHANCEMENTS (R)
WSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
R
7
Locked Block, Operation Abort
STATUS (BEFCES)
STATUS (PBPSS)
OTP PROGRAM STATUS (PBPOPS)
BESS
14
R
6
BEFCES
13
R
5
Table 7. Status Register Definition
PBPOPS
12
R
4
LHF32FDH
Check SR.7 to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, page buffer program, set/clear block lock bit, set block
lock-down bit, attempt, an improper command sequence was
entered.
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and
should be masked out when polling the status register.
11
R
R
3
PBPSS
10
R
2
NOTES:
DPS
R
9
1
Rev. 2.41
R
R
8
0
12